One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

• US 20040061148A1
• Filed: 09/30/2003
• Published: 04/01/2004
• Est. Priority Date: 03/11/2002
• Status: Active Grant

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Monolithic System Technology
• Inventors: Hsu, Fu-Chieh
• Granted Patent: US 6,913,964 B2
• Time in Patent Office: Days
• US Class Current: 257/239
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.

Claims

1. A method of operating a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell having an underlying buried region, the method comprising:

biasing the buried region; and

writing a data bit to the 1T/FB DRAM cell using a hot carrier injection mechanism.

2. A method of operating a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell having an underlying buried region, the method comprising:

biasing the buried region; and

writing a data bit to the 1T/FB DRAM cell using a junction forward bias mechanism.

3. A method of fabricating a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell, method comprising:

forming a buried region having a first conductivity type below an upper surface of a semiconductor region of a semiconductor substrate, the semiconductor region having a second conductivity type, opposite the first conductivity type; and

forming a field-effect transistor in the semiconductor region over the buried region, wherein a depletion region is located between the buried region and source, drain and body regions of the field-effect transistor.

4. The method of claim 3, wherein the buried region is formed by an ion implantation step.

5. The method of claim 4, wherein the buried region is implanted through a first mask.

6. The method of claim 5, further comprising performing a threshold voltage adjustment implant having the second conductivity type through the first mask.

7. The method of claim 3, further comprising forming one or more shallow trench isolation regions that extend a first depth into the semiconductor substrate.

8. The method of claim 7, further comprising implanting the buried region such that the buried region has a top interface located at or above the first depth in the semiconductor substrate, and a bottom interface located below the first depth in the semiconductor substrate.

9. The method of claim 3, wherein the field-effect transistor is fabricated using a process compatible with a standard CMOS process.

10. The method of claim 3, further comprising forming a well region having the first conductivity type in the semiconductor substrate, wherein the buried region contacts the well region.

11. The method of claim 3, further comprising forming a deep well region having the first conductivity type in the semiconductor substrate, wherein the deep well region is located below and continuous with the buried region.

12. The method of claim 11, further comprising forming a well region having the first conductivity type in the semiconductor substrate, wherein the well region contacts the deep well region.