Memory array employing single three-terminal non-volatile storage elements

• US 20040062075A1
• Filed: 09/27/2002
• Published: 04/01/2004
• Est. Priority Date: 09/27/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reohr, William Robert, Wang, Li-Kong
• Granted Patent: US 6,894,916 B2
• Time in Patent Office: Days
• US Class Current: 365/185.01
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

An improved non-volatile memory array comprises a plurality of memory cells, at least one of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell. The memory array further comprises a plurality of write lines operatively coupled to the memory cells for selectively writing the logical state of one or more memory cells in the memory array, and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing the logical state of one or more memory cells in the memory array. The memory array is advantageously configured so as to eliminate the need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell.

Claims

1. A non-volatile memory array, comprising:

a plurality of memory cells, at least one of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell;

a plurality of write lines operatively coupled to the memory cells for selectively writing one or more memory cells in the memory array; and

a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing one or more memory cells in the memory array;

wherein the memory array is configured so as to eliminate a need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell.

2. The memory array of claim 1, wherein:

the word lines are arranged substantially orthogonal to the bit lines; and

the write lines are arranged substantially diagonal with respect to the word lines and bit lines, such that no two memory cells coupled to a same write line share a same word line or bit line.

3. The memory array of claim 2, wherein each of at least a portion of the memory cells is operatively coupled at an intersection of a bit line and a corresponding word line.

4. The memory array of claim 1, wherein:

the word lines are arranged substantially orthogonal with respect to the bit lines; and

the write lines are arranged substantially parallel to at least one of the word lines and bit lines.

5. The memory array of claim 1, wherein a first terminal of the non-volatile storage element is coupled to a corresponding write line, a second terminal of the non-volatile storage element is coupled to a corresponding word line and a third terminal of the non-volatile storage element is coupled to a corresponding bit line.

6. The memory array of claim 1, wherein the at least one memory cell is selectively operable in at least:

a first mode, wherein a logical state of the at least one memory cell is read; and

a second mode, wherein the at least one memory cell is written to a predetermined logical state.

7. The memory array of claim 6, wherein the first mode comprises determining a conductance of a region between the second and third terminals of the non-volatile storage element, the conductance being representative of the logical state of the at least one memory cell.

8. The memory array of claim 7, wherein during the first mode of operation, the conductance of the region between the second and third terminals in the non-volatile storage element is determined by performing at least one of:

applying a predetermined voltage potential across the second and third terminals of the non-volatile storage element and substantially concurrently measuring a current flowing through the region between the second and third terminals of the non-volatile storage element; and

applying a predetermined current through the region between the second and third terminals of the non-volatile storage element and substantially concurrently measuring a voltage across the second and third terminals of the non-volatile storage element.

9. The memory array of claim 6, wherein the non-volatile storage element is a ferroelectric gate field-effect transistor (FeGFET), the first terminal being a gate terminal of the FeGFET, the second terminal being a first drain/source tenninal of the FeGFET, and the third terminal being a second drain/source terminal of the FeGFET.

10. The memory array of claim 9, wherein during the second mode of operation, the logical state of the at least one memory cell is written by applying a voltage potential between the gate terminal of the FeGFET and at least one of the first and second drain/source terminals of the FeGFET, such that an electric field is generated in a ferroelectric gate dielectric layer in the FeGFET which is at least equal to a coercive field associated with the ferroelectric gate dielectric layer, whereby the logical state of the memory cell is stored in the FeGFET, the logical state being determined at least in part by a direction of the applied electric field.

11. The memory array of claim 9, wherein the second mode comprises:

applying a first voltage to at least one of the first drain/source terminal and the second drain/source terminal of the FeGFET, the first voltage having a magnitude less than a coercive voltage V_C of the ferroelectric gate dielectric layer in the FeGFET; and

applying a second voltage to the gate terminal of the FeGFET, the second voltage having a magnitude and polarity which, when summed with the first voltage, results in a voltage potential at least equal to the coercive voltage V_C of the ferroelectric gate dielectric layer in the FeGFET.

12. The memory array of claim 11, wherein the first voltage has a potential substantially equal to one-half of the coercive voltage (V_C/2), and the second voltage has a potential substantially equal to one-half the coercive voltage and a polarity which is opposite a polarity of the first voltage (−

V_C/2).

13. The memory array of claim 6, wherein the at least one memory cell is further selectively operable in at least a third mode, wherein a voltage potential at the first, second and third terminals of the non-volatile storage element are substantially equal, thereby maintaining the logical state of the at least one memory cell.

14. The memory array of claim 1, wherein at least two memory cells are stacked on top of one another in a vertical dimension.

15. A method of forming a non-volatile memory array, comprising the steps of:

providing a plurality of memory cells, at least one memory cell comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell; and

coupling the memory cells to a plurality of write lines, bit lines and word lines for selectively reading and writing the logical state of one or more memory cells in the memory array, the memory cells being operatively coupled to the write lines, bit lines and word lines so as to eliminate a need for a pass gate being coupled to a corresponding non-volatile storage element in the at least one memory cell.

16. The method of claim 15, wherein the step of coupling the memory cells to the plurality of write lines, bit lines and word lines comprises:

connecting a first terminal of each non-volatile storage element to a corresponding write line;

connecting a second terminal of each non-volatile storage element to a corresponding word line; and

connecting a third terminal of each non-volatile storage element to a corresponding bit line.

17. The method of claim 15, further comprising the steps of:

arranging at least a portion of the plurality of word lines to be substantially orthogonal to at least a portion of the plurality of bit lines; and

arranging at least a portion of the plurality of write lines to be substantially diagonal with respect to the word and bit lines, such that no two memory cells coupled to a same write line share a same word line or bit line.

18. The method of claim 15, further comprising the steps of:

during a first mode of operation, selectively reading a logical state of the at least one memory cell; and

during a second mode of operation, selectively writing a logical state of the at least one memory cell.

19. The method of claim 18, wherein the step of reading the logical state of the at least one memory cell comprises determining a conductance of a region between the second and third terminals of the non-volatile storage element, the conductance being representative of the logical state of the at least one memory cell.

20. The method of claim 19, wherein the step of determining the conductance of a channel region comprises at least one of:

applying a predetermined voltage potential across the second and third terminals of the non-volatile storage element and substantially concurrently measuring a current flowing through the region between the second and third terminals of the non-volatile storage element; and

applying a predetermined current through the region between the second and third terminals of the non-volatile storage element and substantially concurrently measuring a voltage across the second and third terminals of the non-volatile storage element.

21. The method of claim 18, wherein the non-volatile storage element is a ferroelectric gate field-effect transistor (FeGFET), the first terminal being a gate terminal of the FeGFET, the second terminal being a first drain/source terminal of the FeGFET, and the third terminal being a second drain/source terminal of the FeGFET.

22. The method of claim 21, wherein the step of writing the logical state of the at least one memory cell comprises generating an electric field in a ferroelectric gate dielectric layer in the FeGFET which is at least equal to a coercive field associated with the ferroelectric gate dielectric layer, whereby the logical state of the memory cell is stored in the FeGFET, the logical state being determined at least in part by a direction of the electric field.

23. The method of claim 21, wherein the step of writing the logical state of the at least one memory cell comprises:

applying a first voltage to at least one of the first drain/source terminal and the second drain/source terminal of the FeGFET, the first voltage having a magnitude less than a coercive voltage V_C of the ferroelectric gate dielectric layer in the FeGFET; and

applying a second voltage to the gate terminal of the FeGFET, the second voltage having a magnitude and polarity which, when summed with the first voltage, results in a voltage potential across the ferroelectric gate dielectric layer in the FeGFET at least equal to the coercive voltage V_C of the ferroelectric gate dielectric layer.

24. The method of claim 23, wherein the first voltage has a potential substantially equal to one-half of the coercive voltage (V_C/2), and the second voltage has a potential substantially equal to one-half the coercive voltage and a polarity which is opposite a polarity of the first voltage (−

V_C/2).

25. The method of claim 15, further comprising the step of stacking two or more memory cells on top of one another in a vertical dimension.

26. A memory cell for use in a memory array including a plurality of bit lines, word lines and write lines, the memory cell comprising:

a non-volatile storage element for storing a logical state of the memory cell, the non-volatile storage element including first, second and third terminals;

wherein the first, second and third terminals of the non-volatile storage element are operatively coupled to a corresponding bit line, word line and write line, respectively, in the memory array so as to eliminate a need for a pass gate being coupled to the non-volatile storage element.