Implantable medical device with hardware-based patch

• US 20040064165A1
• Filed: 09/30/2002
• Published: 04/01/2004
• Est. Priority Date: 09/30/2002
• Status: Abandoned Application

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Thompson, David L.
• Application Number:
  US10/260,943
• Publication Number:
  US 20040064165A1
• Time in Patent Office: Days
• US Class Current: 607/59
• CPC Class Codes: A61N 1/37211 Means for communicating with stimulators
• CPC Class Codes: A61N 1/37264 Changing the program; Upgrading firmware
• CPC Class Codes: G06F 8/60 Software deployment

Abstract

An implantable medical device is provided which provides for more flexibility in re-programming of the control software, or program, which is controlling the functionality of an implanted pacemaker. The system comprises an external programmer device, which is capable both of programming the implanted device in a conventional way, and also downloading new control software to the implanted device. The downloaded software is programmed into a PLD integrated into the microprocessor, I/O, memory, and a clock control system via a standard data bus. The PLD may be configured to modify the function of the microprocessor, system I/O, random logic, and/or firmware function. The system enables increased processing capabilities, speed, flexibility, and attenuation of battery current drain.

Claims

1. A programmable logic device (PLD) implanted in an implantable medical device (IMD) wherein a microcomputer circuit integrates the PLD with a base processor of the IMD, the microcomputer circuit comprising:

a PLD connected to a bus in the base processor;

a plurality of system clocks; and

a memory bank including I/O;

said PLD being operable to store downloaded software from an external programmer device to thereby reprogram the IMD in cooperation with said plurality of system clocks and said memory bank including I/O.

2. The circuit of claim 1 wherein said PLD further comprises:

a configurable block; and

a memory block.

3. The circuit of claim 2 wherein the memory block includes one of an SRAM, EEPROM and flash or FRAM based memory.

4. The circuit of claim 2 wherein the configurable block includes one of the type of field programmable gate array (FPGA), a system programmable gate array (SPGA), a programmable array logic circuit (PAL) and a programmable logic array circuit (PLA).

5. The circuit of claim 2 wherein said configurable block includes means for increasing system processing and speed of the base processor.

6. The circuit of claim 2 wherein said configurable block includes random glue logic to increase functionality of the base processor and reduce battery current drain.

7. The circuit of claim 2 wherein said configurable block includes means for increasing processor power of the base processor and reduce battery current drain.

8. The circuit of claim 7 wherein said means for increasing processor power includes means for modifying the base processor OP codes.

9. The circuit of claim 2 wherein said configurable block includes means for modifying the I/O to enable one of and combinations of extensibility of function and additional product family.

10. The circuit of claim 1 wherein temporary download of clinical studies, algorithmic development, diagnostic data gathering and system self-test are implemented in cooperation with said PLD, said plurality of system clocks and said memory block including I/O.

11. The circuit of claim 1 wherein said plurality of clocks control the base processor and the PLD.

12. The circuit of claim 1 wherein said clocks control one of and a combination of function to slow, stop and synchronize the base processor and the PLD.

13. The circuit of claim 11 wherein said plurality of clocks operates to turn power off to the PLD when not in use.