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EEPROM and EEPROM manufacturing method

  • US 20040070022A1
  • Filed: 09/12/2003
  • Published: 04/15/2004
  • Est. Priority Date: 10/09/2002
  • Status: Active Grant
First Claim
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1. An EEPROM having a memory transistor, said memory transistor comprising:

  • a drain region of a second conductivity type formed in a superficial layer of a semiconductor substrate of a first conductivity type, said drain region including an embedded layer and a drain side field moderating layer formed adjacent to said embedded layer;

    a source region of the second conductivity type in the superficial layer of said semiconductor substrate;

    a channel region between said drain region and said source region;

    a gate insulating film formed on a surface of said semiconductor substrate;

    a tunnel film formed in a part of said gate insulating film above said embedded layer;

    a floating gate electrode formed above said tunnel film and said channel region and having a shape such that it has a size enough to cover said tunnel film and has a gate length approximately equal to a length of said channel region between said drain region and said source region;

    an interlayer insulating film covering an upper face and side faces of said floating gate electrode; and

    a control gate electrode formed above said floating gate electrode interposing said interlayer insulating film therebetween.

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