EEPROM and EEPROM manufacturing method
First Claim
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1. An EEPROM having a memory transistor, said memory transistor comprising:
- a drain region of a second conductivity type formed in a superficial layer of a semiconductor substrate of a first conductivity type, said drain region including an embedded layer and a drain side field moderating layer formed adjacent to said embedded layer;
a source region of the second conductivity type in the superficial layer of said semiconductor substrate;
a channel region between said drain region and said source region;
a gate insulating film formed on a surface of said semiconductor substrate;
a tunnel film formed in a part of said gate insulating film above said embedded layer;
a floating gate electrode formed above said tunnel film and said channel region and having a shape such that it has a size enough to cover said tunnel film and has a gate length approximately equal to a length of said channel region between said drain region and said source region;
an interlayer insulating film covering an upper face and side faces of said floating gate electrode; and
a control gate electrode formed above said floating gate electrode interposing said interlayer insulating film therebetween.
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Abstract
A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.
40 Citations
17 Claims
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1. An EEPROM having a memory transistor, said memory transistor comprising:
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a drain region of a second conductivity type formed in a superficial layer of a semiconductor substrate of a first conductivity type, said drain region including an embedded layer and a drain side field moderating layer formed adjacent to said embedded layer;
a source region of the second conductivity type in the superficial layer of said semiconductor substrate;
a channel region between said drain region and said source region;
a gate insulating film formed on a surface of said semiconductor substrate;
a tunnel film formed in a part of said gate insulating film above said embedded layer;
a floating gate electrode formed above said tunnel film and said channel region and having a shape such that it has a size enough to cover said tunnel film and has a gate length approximately equal to a length of said channel region between said drain region and said source region;
an interlayer insulating film covering an upper face and side faces of said floating gate electrode; and
a control gate electrode formed above said floating gate electrode interposing said interlayer insulating film therebetween. - View Dependent Claims (2, 3)
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4. An EEPROM of a floating gate type and a two-layer polysilicon type having a memory transistor and a select transistor for selecting said memory transistor, said memory transistor comprising:
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an embedded layer of a second conductivity type formed in a superficial layer of a semiconductor substrate of a first conductivity type;
a drain side field moderating layer of the second conductivity type formed adjacent to said embedded layer in the superficial layer of said semiconductor substrate;
a source region of the second conductivity type in the superficial layer of said semiconductor substrate;
a channel region between said drain side field moderating layer and said source region;
a gate insulating film formed on a surface of said semiconductor substrate;
a tunnel film formed in a part of said gate insulating film above said embedded layer;
a floating gate electrode formed above said tunnel film and said channel region and having a shape such that it entirely covers said tunnel film and covers neither said source region nor said drain side field moderating layer;
an interlayer insulating film covering an upper face and side faces of said floating gate electrode; and
a control gate electrode formed above said floating gate electrode interposing said interlayer insulating film therebetween, wherein said source region and said drain side field moderating layer are self-aligningly formed by ion implantation using said floating gate electrode as a mask, and wherein said control gate electrode is shaped to be wider than said floating gate electrode and to wrap said floating gate electrode above said tunnel film and is shaped to be narrower than said floating gate electrode above said channel region. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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11. A manufacturing method of a floating gate type EEPROM having a memory transistor and a select transistor for selecting said memory transistor, said manufacturing method comprising the steps of:
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forming an embedded layer of a second conductivity type in a region where said memory transistor is to be formed in a semiconductor substrate of a first conductivity type;
forming a gate insulating film on a surface of said semiconductor substrate in which said embedded layer has been formed;
exposing the surface of said semiconductor substrate through said gate insulating film by etching a part of said gate insulating film on said embedded layer;
forming a tunnel film on the exposed surface of said semiconductor substrate;
forming a floating gate electrode by forming a first polysilicon layer on said gate insulating film and said tunnel film and then patterning it, said floating gate electrode having a shape such that it covers the entirety of said tunnel film and a channel formation region where a channel region is to be formed and does not cover a region between said channel formation region and said embedded layer and a source formation region where a source region is to be formed;
forming a drain side field moderating layer of the second conductivity type adjacently to said embedded layer and self-aligningly by implanting ions into the region between said channel formation region and said embedded layer with said floating gate electrode used as a mask;
forming an interlayer insulating film so as to entirely cover an upper face and side faces of said floating gate electrode;
forming a control gate electrode by forming a second polysilicon layer on said interlayer insulating film in a state where said interlayer insulating film entirely covers the upper face and side faces of said floating gate electrode and then patterning it, said control gate electrode having a shape such that, above said tunnel film, it is wider than said floating gate electrode and wraps said floating gate electrode, and, above said channel formation region, it is narrower than said floating gate electrode and does not cover said drain side field moderating layer; and
forming a source region self-aligningly by implanting ions into a superficial layer of said semiconductor substrate with said floating gate electrode used as a mask so that said channel region is formed between said drain side field moderating layer and said source region. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification