Semiconductor device and fabrication method of the same

• US 20040070064A1
• Filed: 10/09/2003
• Published: 04/15/2004
• Est. Priority Date: 10/15/2002
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Yamane, Tae, Fukaya, Kiyohisa, Katsuno, Jyouji
• Granted Patent: US 7,045,899 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device includes semiconductor chips, a first conductive pattern, an external terminal and an encapsulating resin. Each of the semiconductor chips has a front side formed with integrated circuits and a back side. The semiconductor chips are stacked each other. The first conductive pattern electrically connects the integrated circuits. The external terminal is electrically connected to the first conductive pattern. The encapsulating resin encapsulates the semiconductor chips and the first conductive pattern.

Claims

1. A semiconductor device comprising:

a plurality of semiconductor chips each of which has a front side formed with a plurality of integrated circuits and a back side, the semiconductor chips being stacked;

a first conductive pattern electrically connecting the integrated circuits;

an external terminal electrically connected to the first conductive pattern; and

an encapsulating resin for encapsulating the semiconductor chips and the first conductive pattern.

2. The semiconductor device according to claim 1, wherein the semiconductor chips include first and second semiconductor chips, the second semiconductor chip is mounted on the first semiconductor chip as the back side of the second semiconductor chip faces the front side of the first semiconductor chip, and a passivation film is formed on the front side of the second semiconductor chip.

3. The semiconductor device according to claim 1, wherein the semiconductor chips include first and second semiconductor chips, and the second semiconductor chip is mounted on the first semiconductor chip as the back side of the second semiconductor chip faces the front side of the first semiconductor chip, and wherein the semiconductor device further includes a plurality of pad electrodes formed on the front side of the first semiconductor chip and electrically connected to the integrated circuits, a second conductive pattern for connecting the adjacent pad electrodes, and a post electrode formed on the second conductive pattern for electrically connecting between the second conductive pattern and the external terminal.

4. The semiconductor device according to claim 3, wherein the post electrode is formed near almost a center part of the second wiring.

5. The semiconductor device according to claim 1, wherein the semiconductor chips include first and second semiconductor chips, the second semiconductor chip is mounted on the first semiconductor chip as the back side of the second semiconductor chip faces the front side of the first semiconductor chip, and wherein the semiconductor device further includes

a first post electrode formed on the first conductive pattern for electrically connecting between the first wiring and the external terminal, and

a second post electrode formed on the front side near the periphery of the first semiconductor chip simultaneously with the first post electrode, the second post electrode for recognizing the periphery of the first semiconductor chip.

6. The semiconductor device according to claim 1, wherein the semiconductor chips include first and second semiconductor chips, the second semiconductor chip is mounted on the first semiconductor chip as the front side of the second semiconductor chip faces the front side of the first semiconductor chip, and wherein the semiconductor device further includes

a plurality of post electrodes for electrically connecting between the first conductive pattern and the external terminal, the plurality of the post electrodes formed on the first conductive pattern so as to surround the second semiconductor chip,

a first encapsulating resin for encapsulating the periphery of the post electrodes, and

a second encapsulating resin for encapsulating the second semiconductor chip.

7. The semiconductor device according to claim 1, wherein the semiconductor chips include first and second semiconductor chips, the second semiconductor chip has a first encapsulating resin formed on the front side of the second semiconductor chip, and a projecting electrode electrically connected to the integrated circuit of the second semiconductor chip and projecting from the first encapsulating resin, and the second semiconductor chip is mounted on the semiconductor chip so as to connect to the first conductive pattern.

8. The semiconductor device according to claim 7, wherein the first conductive pattern is provided with an opening part, and the projecting electrode is placed on the opening part of the first conductive pattern.

9. The semiconductor device according to claim 7, wherein the first conductive pattern is provided with a recess, and the projecting electrode is placed on the recess of the first conductive pattern.

10. The semiconductor device according to claim 7, wherein the projecting electrode is connected to the first conductive pattern through an adhesive material.

11. The semiconductor device according to claim 1, wherein the semiconductor devices includes first and second semiconductor chips, and the front side of the second semiconductor chip is connected to the front side of the first semiconductor chip through an adhesive material.

12. The semiconductor device according to claim 1, wherein the semiconductor chips includes first to third semiconductor chips, the second semiconductor chip is mounted on the first semiconductor chip as the front side of the second semiconductor chip faces the front side of the first semiconductor chip, and the third semiconductor chip is mounted on the second semiconductor chip as the back side of the third semiconductor chip faces the back side of the second semiconductor chip.