Synchronization error detection circuit

• US 20040078737A1
• Filed: 06/27/2003
• Published: 04/22/2004
• Est. Priority Date: 07/01/2002
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Miyamoto, Hiromitsu
• Granted Patent: US 7,174,502 B2
• Time in Patent Office: Days
• US Class Current: 714/700
• CPC Class Codes: H03M 13/33 Synchronisation based on error coding or decoding
• CPC Class Codes: H04L 1/1812 Hybrid protocols; Hybrid automatic repeat request [HARQ]
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/043 Pseudo-noise [PN] codes variable during transmission synchronisation of spread spectrum receivers H04B1/69

Abstract

Synchronization errors in a received pulse train are detected by detecting rising or falling transitions in the pulse train, generating numbers in a repeating cycle having a length corresponding to the pulse rate, selecting the number generated when each transition is detected, and performing a predetermined operation on the selected numbers. The predetermined operation may include, for example, comparing the average values of the selected numbers in successive groups of transitions. Alternatively, the predetermined operation may include taking a difference between consecutively selected numbers to measure pulse widths in the pulse train. Synchronization error detection can be used to supplement data error detection and correction methods such as forward error correction and cyclic redundancy checks.

Claims

1. A synchronization error detection circuit for detecting errors due to faulty synchronization with a received pulse train, comprising:

a transition detector for detecting rising or falling transitions of pulses constituting the received pulse train;

a cyclic number generator for generating numbers that repeat cyclically over a predetermined time corresponding to a rate at which said pulses arrive in the received pulse train;

a selector for selecting a number generated by the cyclic number generator when a transition is detected by the transition detector, thereby associating the selected number with the detected transition; and

a synchronization error detector for carrying out a predetermined operation on the numbers selected by the selector, thereby detecting synchronization errors.

2. The synchronization error detection circuit of claim 1, wherein the synchronization error detector detects said synchronization errors by using the numbers selected by the selector to calculate average values over groups of transitions, and comparing successive average values.

3. The synchronization error detection circuit of claim 2, wherein the synchronization error detector includes a decision circuit that compares a difference between said successive average values with a predetermined threshold value, a synchronization error being detected when the difference exceeds the predetermined threshold value.

4. The synchronization error detection circuit of claim 2, wherein the synchronization error detector includes an averaging circuit that, for each group of transitions among said groups of transitions, takes differences between the selected number associated with a first transition in the group and the selected numbers associated with the subsequent transitions in the group, adds said differences to obtain a sum, divides the sum by the number of transitions in the group to obtain a quotient, and adds the quotient to the selected number associated with the first transition in the group.

5. The synchronization error detection circuit of claim 1, wherein the synchronization error detector includes a pulse width measuring circuit taking a difference between the selected numbers associated with a consecutive pair of said transitions, thereby obtaining a pulse width value.

6. The synchronization error detection circuit of claim 5, wherein the synchronization error detector further includes a decision circuit for comparing said pulse width value with a predetermined threshold value.

7. The synchronization error detection circuit of claim 6, wherein a synchronization error is detected when the pulse width value is less than the predetermined threshold value.

8. The synchronization error detection circuit of claim 1, further comprising a retransmission request generator for sending a retransmission request to a transmitting source of said received pulse train when a synchronization error is detected.

9. A method of detecting synchronization errors in a received pulse train, comprising:

detecting rising or falling transitions of pulses constituting the received pulse train;

generating phase numbers that repeat cyclically over a predetermined time corresponding to a rate at which said pulses arrive in the received pulse train;

selecting the phase number generated when each transition is detected, thereby associating the selected phase number with the detected transition; and

carrying out a predetermined operation on the selected phase numbers, thereby detecting synchronization errors.

10. The method of claim 9, wherein the predetermined operation comprises:

using the selected phase numbers to calculate average values over groups of transitions; and

comparing successive average values.

11. The method of claim 10, wherein the predetermined operation further comprises:

taking a difference between a pair of said successive average values; and

comparing said difference with a predetermined threshold value, a synchronization error being detected when the difference exceeds the predetermined threshold value.

12. The method of claim 10, wherein using the selected phase numbers to calculate average values further comprises, for each group of transitions among said groups of transitions:

taking differences between the selected phase number associated with a first transition in the group and the selected phase numbers associated with the subsequent transitions in the group;

adding said differences to obtain a sum;

dividing said sum by the number of transitions in the group to obtain a quotient; and

adding the quotient to the selected number associated with the first transition in the group.

13. The method of claim 9, wherein the predetermined operation includes taking a difference between the selected phase numbers associated with a consecutive pair of said transitions, thereby obtaining a pulse width value.

14. The method of claim 13, wherein the predetermined operation further includes comparing said pulse width value with a predetermined threshold value.

15. The method of claim 14, wherein a synchronization error is detected when the pulse width value is less than the predetermined threshold value.

16. The method of claim 9, further comprising sending a retransmission request to a transmitting source of said received pulse train when a synchronization error is detected.

17. The method of claim 9, further comprising disabling detection of data errors in the received pulse train when a synchronization error is detected.

18. The method of claim 9, further comprising disabling correction of data errors in the received pulse train when a synchronization error is detected.