VARIABLE CHARGE PUMP CIRCUIT WITH DYNAMIC LOAD

• US 20040080360A1
• Filed: 01/27/2003
• Published: 04/29/2004
• Est. Priority Date: 10/25/2002
• Status: Active Grant

• Current Assignee: Nera Innovations Limited (Atlantic IP Services Limited)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Bedarida, Lorenzo, Sivero, Stefano, Bartoli, Simone
• Granted Patent: US 6,724,241 B1
• Time in Patent Office: Days
• US Class Current: 327/536
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A variable charge pump circuit uses a plurality of selectable loads to minimize the voltage ripples of the pumped output by selecting the appropriate load for a preselected pump voltage. The charge pump circuit also compares the pump voltage to a reference voltage to shut down the variable charge pump circuit if the pump voltage is larger than the reference voltage. The charge pump circuit also compares the maximum voltage output to the reference voltage to monitor whether the maximum ripple on voltage output is larger than the reference voltage. The charge pump circuit comprises one or more stages operable to receive a supply voltage and generate one or more pump voltages, a plurality of loads each associated with a specific pump voltage, and a load selector means coupled to the output pump and the plurality of loads for selecting a load associated with a specific pump voltage.

Claims

1. A charge pump circuit for generating a charge pump voltage having minimal voltage ripples, comprising:

a) a pumping circuit comprising one or more stages operable to receive a supply voltage and generate a selected one of a plurality of pump voltages;

b) a plurality of loads selectively coupleable to an output of the pumping circuit, each load associated with a specific pump voltage; and

c) a load selector means for selectively coupling a load associated with a specific pump voltage to the output of said pumping circuit.

2. The charge pump circuit of claim 1, wherein the load selector means includes a target output pump selector for shutting down the variable charge pump circuit when the target output pump voltage (Vcfra) is greater than or equal to a reference voltage (Vref).

3. The charge pump circuit of claim 2, wherein the load selector means further includes a maximum ripple on the target output selector means for adding a load, whenever a maximum ripple on the target output voltage (Vcfrb) greater than the reference voltage (Vref) then the maximum ripple on the target output selector means adds additional loads until the Vcfrb voltage is less than or equal to the reference voltage (Vref).

4. The charge pump circuit of claim 1, wherein the pumping circuit comprises:

a) a plurality of diodes coupled in series, each diode having an input terminal and an output terminal, the input terminal of the first diode in the series is coupled to the supply voltage, the output of the first diode being connected to the input terminal of the second diode, and the output terminal of the last diode connected to the output pump;

b) a plurality of capacitors having a first terminal and a second terminal, wherein the first terminal of the first capacitor being coupled to the output of a first diode and the input of a second diode, the first terminal of the second capacitor being coupled to the output of the second diode and the input of a third diode, and the first terminal of the last capacitor is coupled to the input terminal of a last diode;

c) a plurality of inverters coupled in series to one another, each having an input terminal and an output terminal, the output of the first inverter being coupled to the second terminal of the first capacitor forming the first stage of the charge pump circuit, the second output of the second inverter coupled to the second terminal of the second capacitor forming the second stage of the charge pump circuit, and the output of the last inverter is coupled to the second terminal of the last capacitor forming the last stage of the charge pump circuit; and

d) a clock signal coupled to the input terminal of the first inverter.

5. The variable charge pump circuit of claim 4, wherein each of the plurality of diodes is a diode-connected NMOS transistor, the gate of each transistor being connected to its drain forming the input terminal and its source forming the second terminal.

6. The charge pump circuit of claim 1, wherein the load selector means is a plurality of switches, one switch for each of said loads, each switch having a first terminal, a second terminal, and an enable terminal, the switch being coupled in series with each load, the first terminal of the switch being coupled to the output pump and the second terminal of the switch is coupled to each load.

7. The charge pump circuit of claim 1, wherein each load selector means comprises an NMOS transistor having a gate, a drain and a source, the gate of the NMOS load transistor being coupled to an enable signal, the source of the load NMOS load transistor being coupled to an electrical ground, and the drain being coupled to a load.

8. The charge pump circuit of claim 7, wherein each load is a capacitor or a current sinker having a first terminal and a second terminal, the first terminal being coupled to the pump voltage and the second terminal being coupled to the drain of the NMOS transistor.

9. The charge pump circuit of claim 1 wherein each load selector means comprises an elevator circuit having an input terminal and an output terminal, the input terminal being coupled to an enable signal, the output terminal being coupled to a load NMOS transistor, the gate of the load NMOS transistor being connected to the output terminal of the elevator circuit, the drain of the NMOS transistor being coupled to the pump output, and the source being coupled to the load.

10. The charge pump circuit of claim 9, wherein each load is a capacitor or a current sinker having a first terminal and a second terminal, the first terminal being coupled to the source of the NMOS transistor and the second terminal being coupled to an electrical ground.

11. The charge pump circuit of claim 2 wherein the target output pump selector comprises:

a) a first comparator having two input terminals, an output terminal and a first enable terminal, one of the two input terminals being connected to the reference voltage (Vref);

b) a first resistor network having two terminals, the first terminal being coupled to the output pump, the second terminal being coupled to one of the input terminals of the first comparator;

c) a second resistor network having two terminals, the first terminal being coupled to the second terminal of the first resistor network, and the second terminal of the second resistor network being coupled to an electrical ground; and

d) a reference voltage source (Vref) coupled to one of the input terminals of the first comparator.

12. The charge pump circuit of claim 11, wherein the maximum overshoot on target output selector means comprises:

a) a third resistor network having two terminals, the first terminal is coupled to the output pump;

b) a fourth resistor network having two terminals, the first terminal is coupled to second terminal of the third resistor network, and the second terminal of the fourth resistor network being coupled to an electrical ground;

c) a second comparator having two input terminal, an output terminal, and an enable terminal, one of the input terminals being coupled to the input terminal of the fourth resistor network and the other of the input terminals being coupled to the reference voltage Vref;

d) a logic circuit having two terminals, the first terminal is coupled to the output terminal of the second comparator; and

e) a set load coupled to the pump output and being controlled by the logic circuit for adding an additional load to the output pump when the output pump has an overshoot greater than a maximum allowed on the output terminal.

13. A memory device, comprising:

an address bus;

a control circuit;

a data bus;

an address decoder coupled to the address bus;

a read/write circuit coupled to the data bus;

a memory cell array coupled to the address decoder, control circuit, and read/write circuit; and

a charge pump circuit that generates a boosted output voltage with minimum ripples on an output node coupled to the address decoder, read/write circuit, and memory cell array, the charge pump circuit comprising;

a) a pumping circuit comprising one or more stages operable to receive a supply voltage and generate one or more pump voltages;

b) a plurality of loads, each load associated with a specific pump voltage and selectively coupleable to an output of the pump circuit (output pump);

c) a load selector means coupled to the output pump for selecting a load that satisfies a specific pump voltage;

d) a target output pump selector sampling the output of the pump circuit for shutting down the variable charge pump circuit whenever the sampled output voltage (vcfra) is greater than or equal to a reference voltage (Vref);

e) a maximum ripple on target output selector means sampling the output of the pump circuit for adding a load, whenever a maximum ripple on sampled output voltage (Vcfrb) is greater or equal to than the reference voltage (Vref) then the output selector means adds additional loads until the Vcfrb voltage is less than the reference voltage (Vref).

14. A memory system of claim 13, wherein the pumping circuit comprises:

a) a plurality of diodes coupled in series, each diode having an input terminal and an output terminal, the input terminal of the first diode in the series being coupled to the supply voltage, the output of the first diode being connected to the input terminal of the second diode, and the output terminal of the last diode connected to the output pump voltage;

b) a plurality of capacitors having a first terminal and a second terminal, wherein the first terminal of the first capacitor being coupled to the output of the first diode, the first terminal of the second capacitor being coupled to the output of the second diode, and the first terminal of the last capacitor being coupled to the input terminal of the last diode;

c) a plurality of inverter coupled in series to one another, each having an input terminal and an output terminal, the output of the first inverter being coupled to the second terminal of the first capacitor and the input of the second inverter forming the first stage of the charge pump circuit, the second output of the second inverter coupled to the second terminal of the second capacitor forming the second stage of the charge pump circuit, and the output of the last inverter being coupled to the input of the last diode; and

d) a clock signal coupled to the input terminal of the first inverter.

15. The memory system of claim 13, wherein the plurality of diodes is a NMOS transistor connected as a diode, the gate of each transistor being connected to its drain forming the input terminal and the source forming the second terminal.

16. The memory system of claim 13, wherein the load selector means is a switch having a first and a second terminal coupled in series with each load, the first terminal of the switch being coupled to the output pump and the second terminal of the switch is coupled to the load.

17. The memory system of claim 13, wherein each load selector means comprises an NMOS transistor having a gain a drain and a source, the gate of the NMOS load transistor being coupled to an enable signal, the source of the load NMOS load transistor being coupled to an electrical ground, and the drain being coupled to a load.

18. The memory system of claim 17, wherein the load is a capacitor having a first terminal and a second terminal, the first terminal being coupled to the pump voltage and the second terminal being coupled to the drain of the NMOS transistor.

19. The memory system of claim 13 wherein each load selector means comprises an elevator circuit having an input terminal and an output terminal, the input terminal being coupled to an enable signal, the output terminal being coupled to a load NMOS transistor, the gate of the load NMOS transistor being connected to the output terminal of the elevator circuit, the drain of the NMOS transistor being coupled to the pump output.

20. The memory system of claim 19, wherein each load is a capacitor having a first terminal and a second terminal, the first terminal being coupled to the source of the NMOS transistor and the second terminal being coupled to an electrical ground.

21. The memory system of claim 13, wherein load selector means comprises:

a) a first comparator having two input terminal, an output terminal and a first enable terminal, one of the two input terminals connected to the reference voltage (Vref);

b) a first resistor network having two terminals, the first terminal being coupled to the output pump, the second terminal being coupled to the output terminal of the first comparator;

c) a second resistor network having two terminals, the first terminal is coupled to the second terminal of the first resistor network, and the second terminal of the second resistor network being coupled to an electrical ground;

d) a third resistor network having two terminals, the first terminal being coupled to the output pump;

e) a fourth resistor network having two terminals, the first terminal being coupled to the second terminal of the third resistor network, the second terminal of the fourth resistor network being coupled to ground;

f) a second comparator having two input terminals, and output terminal and an enable terminal, one of the input terminals being coupled to the input terminal of the fourth resistor network and the other of the input terminals being coupled to the reference voltage Vref; and

g) a logic circuit having two terminals, the first terminal coupled to the second comparator.

22. The memory system of claim 21, wherein the pumping circuit comprises:

a) a plurality of capacitors or current sinkers having a first terminal and a second terminal, wherein the first terminal of the first capacitor being coupled to the output of the first diode, the first terminal of the second capacitor being coupled to the output of the second diode, and the first terminal of the last capacitor being coupled to the input terminal of the last diode;

b) a plurality of inverter coupled in series to one another, each having an input terminal and an output terminal, the output of the first inverter being coupled to the second terminal of the first capacitor and the input of the second inverter forming the first stage of the charge pump circuit, the second output of the second inverter coupled to the second terminal of the second capacitor forming the second stage of the charge pump circuit, and the output of the last inverter being coupled to the input of the last diode; and

c) a clock signal coupled to the input terminal of the first inverter.

23. The memory system of claim 13, wherein the memory cell is a flash memory cell.

24. A method for generating an output voltage with minimal ripples in a charge pump circuit, comprising:

a) selecting a output pump voltage (Vpump);

b) turning on a load associated with the selected Vpump; and

c) comparing a target output voltage (Vcfra) with a reference voltage (Vref) whenever the target output voltage greater than the reference voltage, disabling the charge pump circuit;

whenever the target output voltage is less or equal to the voltage reference, leaving the charge pump circuit on.

25. The method of claim 24, further comprises the following steps:

a) comparing a maximum acceptable ripple on output voltage value (Vcfrb) with a reference voltage (Vref) whenever the maximum acceptable ripple output voltage value is greater than the reference voltage, connecting a load until the Vcfrb voltage value is less than or equal to the reference voltage;

b) comparing a minimum acceptable drop on output voltage value (Vcfrc) with the reference voltage(Vref), whenever the minimum acceptable drop on output voltage value is less than the reference voltage, removing a load until the Vcfrc voltage value is greater than the reference voltage.