Power management for spatial power combiners

• US 20040080810A1
• Filed: 10/29/2002
• Published: 04/29/2004
• Est. Priority Date: 10/29/2002
• Status: Active Grant

• Current Assignee: Wavestream Wireless Technologies
• Original Assignee: Wavestream Wireless Technologies
• Inventors: Rollison, Christopher J., Martin, Suzanne C., Rosenberg, James J., Deckman, Blythe C.
• Granted Patent: US 7,110,165 B2
• Time in Patent Office: Days
• US Class Current: 359/333
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H03B 5/1841 the frequency-determining element being a strip line resonator H03B5/1805, H03B5/1817, H03B5/1864 and H03B5/1882 take precedence

Abstract

The present invention discloses a system for improving power management for spatial power combining systems, such as a quasi optical grid array amplifier. One aspect of the invention includes the provision of a patterned conductor on the surface the semiconductor chip that opposes the surface upon which the active devices are disposed. This metal material can be used to both enhance heat removal from the chip and to provide a new and more efficient DC biasing path (with the use of vias) for the active components on the other (front) surface of the chip. Another aspect of the invention is the introduction of a dielectric superstrate that attaches to the front surface of the chip to provide an alternative or complementary heat removal and/or biasing structure to the conventional substrate that is typically attached to the back side of the chip. Various combinations of the above features are disclosed.

Claims

1. A spatial power-combining chip having a front surface and a back surface, comprising:

(a) a plurality of active devices disposed on the front surface of the chip; and

(b) patterned, electrically-conductive material disposed on the back surface of the chip.

2. The chip of claim 1, further including patterned, electrically-conductive material disposed on the front surface of the chip.

3. The structure of claim 1 or 2, further including vias disposed within the chip and between the front and back surfaces for providing a DC power-supplying path to the front surface of the chip.

4. The chip of claim 1, wherein the plurality of active devices comprise a quasi-optical grid array.

5. An integrated, spatial power-combining system, comprising:

(a) a spatial power-combining chip having

(i) a front surface with a plurality of active devices disposed thereon, and

(ii) a back surface with patterned, electrically-conductive material disposed thereon; and

(b) a thermally-conductive, dielectric substrate having a front surface attached to the back surface of the spatial power-combining chip.

6. The system of claim 5, wherein the chip further includes vias disposed between the front surface and patterned, electrically-conductive material on the back surface.

7. The system of claim 5, wherein the front surface of the dielectric substrate includes patterned, electrically-conductive material disposed thereon that is connected to the patterned material on the back surface of the power-combining chip.

8. The system of claim 7, wherein the patterned, electrically-conductive material on the back surface of the power-combining chip is connected to the patterned, electrically-conductive material on the front surface of the substrate with one of a solder bond, a thermo-compression bond, an ultrasonic bond and an electrically-conductive adhesive.

9. The system of claim 5, further including

(c) a thermally-conductive, dielectric superstrate having a back surface joined to the front surface of the spatial power-combining chip.

10. The system of claim 9, wherein the back surface of the dielectric superstrate is joined to the front surface of the power-combining structure via a thermally-conductive dielectric joint disposed therebetween.

11. The system of claim 9, wherein the back surface of the dielectric superstrate includes patterned, electrically-conductive material disposed thereon that is joined to the front surface of the power-combining structure.

12. The system of claim 11, wherein the front surface of the chip further includes patterned, electrically-conductive material.

13. The system of claim 12, further including

vias disposed within the spatial power-combining structure and between the patterns on the front and back surfaces of the structure that provides an electrical path for DC power to the front surface of the chip, and wherein

the patterned, electrically-conductive material disposed on the front surface of the substrate is joined to the patterned, electrically-conductive material disposed on the back surface of the power-combining structure via an electrically-conducting joint, and

the patterned, electrically-conductive material disposed on the back surface of the superstrate is joined to the patterned, electrically-conductive material disposed on the front surface of the power-combining structure via an electrically-conducting joint.

14. The system of claim 5, wherein the plurality of active devices comprise a quasi-optical grid array.

15. An integrated spatial power-combining system, comprising:

(a) a spatial power-combining chip having front and back surfaces and active devices integrated on the front surface; and

(b) a thermally-conductive, dielectric superstrate having a back surface attached to the front surface of the spatial power-combining chip.

16. The system of claim 15, wherein the front surface of the dielectric substrate includes patterned, electrically-conductive material disposed thereon that is connected to the patterned material on the back surface of the power-combining chip.

17. The system of claim 16, wherein the patterned, electrically-conductive material on the back surface of the power-combining chip is connected to the patterned, electrically-conductive material on the front surface of the substrate with one of a solder bond, a thermo-compression bond, an ultrasonic bond and an electrically-conductive adhesive.

18. The system of claim 15, wherein the back surface of the dielectric superstrate includes patterned, electrically-conductive material disposed thereon that is connected to the front surface of the power-combining chip.

19. The system of claim 18, wherein the front surface of the chip further includes patterned, electrically-conductive material that is connected to the patterned, electrically-conductive material on the back surface of the superstrate with one of a solder bond, a thermo-compression bond, an ultrasonic bond and an electrically-conductive adhesive.

20. The system of claim 15, further including

(c) a first thermally-conductive joint disposed between the front surface of the power-combining chip and the back surface of the superstrate.

21. The system of claim 20, further including

(d) a thermally-conductive, dielectric substrate having a front surface attached to the back surface of the chip.

22. The system of claim 21, further including

a thermally-conductive joint disposed between the back surface of the power-combining chip the front surface of the substrate.

23. The system of claim 15, wherein the active devices comprise a quasi-optical grid array.

24. A method of drawing heat away from a spatial power-combining chip having a front surface with heat-generating, active components disposed thereon and a back surface that is connected to a thermally-conducting substrate, comprising:

(a) providing a metal pattern on the back surface of the chip;

(b) providing a metal pattern on the front surface of the substrate; and

(c) joining the metal pattern on the back surface of the chip to the metal pattern on the front surface of the substrate in order to draw heat generated by the active devices away from the chip.

25. A method of drawing heat away from a spatial power-combining chip having a front surface with a plurality of heat-generating active devices disposed thereon, comprising:

(a) providing a thermally-conducting dielectric superstrate having front and back surfaces; and

(b) attaching the front surface of the power-combining chip to the back surface of the superstrate via a thermally-conducting joint.

26. The method of claim 25, wherein the back surface of the thermally-conducting dielectric superstrate includes a metal pattern disposed thereon, and wherein the attaching includes joining the metal pattern disposed on the back surface of the superstrate with the front surface of the chip.

27. The method of claim 26, wherein the front surface of the chip further includes a metal pattern disposed thereon and the metal pattern on the back surface of the superstrate is joined to the metal pattern on the front surface of the chip.

28. A method of providing DC power to active components on a power-combining chip having front and back surfaces, wherein the components are disposed on the front surface of the chip, comprising:

(a) providing a metal pattern on the back surface of the power-combining chip;

(b) selectively connecting one or more of the active components to the metal pattern on the back surface of the chip; and

(c) providing DC power to the metal pattern on the back surface of the chip.

29. The method of claim 28, wherein one or more of the active components are selectively connected to the metal pattern on the back surface of the chip with vias disposed between the front and back surfaces of the power-combining chip.

30. The method of claim 28, further comprising:

providing a thermally-conducting, dielectric substrate having a front surface with a metal pattern disposed thereon;

electrically connecting the metal pattern on the front surface of the dielectric substrate to the metal pattern on the back surface of the power-combining chip; and

supplying DC power to the metal pattern on the front surface of the dielectric substrate.

31. A method of providing DC power to active components on a power-combining chip having front and back surfaces, wherein the components are disposed on the front surface of the chip, comprising:

(a) providing a thermally-conducting dielectric superstrate having a back surface with a metal pattern disposed thereon;

(b) electrically connecting the metal pattern on the back surface of the superstrate to selected components on the front surface of the chip; and

(c) applying DC power to the metal pattern on the back surface of the superstrate.

32. An integrated, semiconductor chip having a front surface and a back surface, wherein the chip cannot properly function with a conducting solid ground plane that covers substantially the entire back surface of the chip, comprising:

(a) a plurality of active devices integrated into the front surface of the chip, and

(b) patterned, electrically-conductive material disposed on the back surface of the chip.

33. The chip of claim 32, wherein the patterned material disposed on the back surface of the chip is a ground.