Structure and method for forming self-aligned bipolar junction transistor with expitaxy base

• US 20040082135A1
• Filed: 10/23/2002
• Published: 04/29/2004
• Est. Priority Date: 10/23/2002
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chuang, Shu-Ya
• Granted Patent: US 6,774,002 B2
• Time in Patent Office: Days
• US Class Current: 438/312
• CPC Class Codes: H01L 29/66287 with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation H01L29/6628 takes precedence

Abstract

The present invention proposes a novel method to fabricate a Bipolar Junction Transistor device. The steps of the present invention include forming a shallow trench isolation structure in a substrate. An oxide layer is formed on the substrate. Subsequently, a polysilicon layer is next formed on the oxide layer, and the polysilicon layer has first type ion. Successively, a polysilicon layer is patterned on the oxide layer. The next step is to perform a second type ion implantation, thereby forming a collector region in the substrate and below the emitter window. The oxide layer is removed inside the emitter window. An expitaxy base is then formed on the polysilicon layer and substrate, thereby forming base region on the collector region, wherein the expitaxy base has the first type ion. After the expitaxy base is formed, a dielectric layer is formed over the expitaxy base. Next, the dielectric layer is etched to form inner spacer on sidewalls of the expitaxy base inside the emitter window. A second polysilicon layer is formed over the expitaxy base and the emitter window, wherein the second polysilicon layer has the second type ion. Finally, an etching process is introduced to etch the second polysilicon layer to form emitter plug. That is self-aligned to the emitter window.

Claims

1. A method for forming a self-aligned Bipolar Junction Transistor with expitaxy base comprising:

forming a oxide layer on a semiconductor substrate;

forming a first polysilicon layer over said oxide layer, said first polysilicon layer with first type ion;

removing said first polysilicon layer partly to expose said oxide layer, thereby forming a emitter window;

performing a second type ion implantation to form a collector region in said substrate and below said emitter window, wherein said second type ion'"'"'s is opposite to said first type ion'"'"'s conductive type;

removing said oxide layer inside said emitter window;

forming a expitaxy base layer over said first polysilicon layer and said semiconductor substrate to form a base region on said collector region, wherein said expitaxy base has said first type ion;

forming a dielectric layer over said expitaxy base;

etching said dielectric layer to form a inner spacer on sidewalls of said expitaxy base inside said emitter window;

forming a second polysilicon layer over said expitaxy base and said emitter window, wherein said second polysilicon layer has second type ion;

and

etching said second polysilicon layer to form emitter plug, that is self-aligned to said emitter window.

2. The method of claim 1, wherein said oxide thickness is 50˜

500 angstrom (Å

).

3. The method of claim 2, wherein said oxide is formed by using chemical vapor deposition (CVD) method.

4. The method of claim 1, wherein said first polysilicon thickness is 2000˜

4000 angstrom (Å

).

5. The method of claim 4, wherein said first polysilicon is formed by using chemical vapor deposition (CVD) method.

6. The method of claim 1, wherein said first type ion is P-type ion.

7. The method of claim 1, wherein said first type ion is N-type ion.

8. The method of claim 1, wherein said second type ion is P-type ion.

9. The method of claim 1, wherein said second type ion is N-type ion.

10. The method of claim 1, wherein said expitaxy base is in-situ doping polysilicon.

11. The method of claim 1, wherein said dielectric layer comprises oxide formed by using chemical vapor deposition (CVD) method.

12. The method of claim 1, wherein said dielectric layer comprises NO (nitride/oxide) formed by using chemical vapor deposition (CVD) method.

13. The method of claim 1, wherein said second polysilicon comprises in-situ doping polysilicon formed by using chemical vapor deposition (CVD) method.

14. The method of claim 1, wherein said second polysilicon comprises forming a first polysilicon, performing a ion implantation to said first polysilicon, forming a second polysilicon, and performing a ion implantation to said second polysilicon.

15. The method of claim 1, wherein said collector region/base region/emitter region of said Bipolar Junction Transistor is P/N/P type.

16. The method of claim 1, wherein said collector region/base region/emitter region of said Bipolar Junction Transistor is N/P/N type.

17. The method of claim 1, further comprising removing parts of said expitaxy base layer and said first ploysilicon layer to form poly base interconnect pattern after forming said emitter plug.

18. The method of claim 17, further comprising performing a rapid thermal annealing process after removing parts of said expitaxy base layer and said first ploysilicon layer.

19. The method of claim 18, further comprising depositing a salicide layer over said expitaxy base layer, said emitter plug and said inner spacer after performing said rapid thermal annealing process.

20. The method of claim 19, further comprising removing parts of said salicide layer to form a patterned salicide layer on said expitaxy base, said emitter plug and over said expitaxy base, said first ploysilicon layer after said depositing salicide layer.

33. The method of claim 1, wherein said emitter plug is in-situ doping polysilicon.

34. The method of claim 33, wherein said second polysilicon comprises forming a first polysilicon, performing a ion implantation to said first polysilicon, forming a second polysilicon, and performing a ion implantation to said second polysilicon.

21. A bipolar junction transistor with expitaxy base comprising:

forming a oxide layer on a semiconductor substrate;

forming a polysilicon layer over said oxide layer, and removing said polysilicon layer partly to form a emitter window on said oxide layer, said polysilicon layer with first type ion;

forming a collector region in said substrate and below said emitter window, wherein said collector region has a second type ion'"'"'s, said second type ion'"'"'s is opposite to said first type ion'"'"'s conductive type;

forming a expitaxy base layer over said first polysilicon layer and said semiconductor substrate to form a base region on said collector region after removing said oxide layer inside said emitter window, wherein said expitaxy base has said first type ion;

forming a inner spacer on sidewalls of said expitaxy base inside said emitter window;

forming a emitter plug over said expitaxy base and said emitter window, wherein said emitter plug has second type ion;

removing parts of said expitaxy base layer and said ploysilicon layer to form poly base interconnect pattern; and

forming a patterned salicide layer on said expitaxy base, said emitter plug and over said expitaxy base, said ploysilicon layer.

22. The method of claim 21, wherein said oxide thickness is 50˜

500 angstrom (Å

).

23. The method of claim 22, wherein said oxide is formed by using chemical vapor deposition (CVD) method.

24. The method of claim 21, wherein said first polysilicon thickness is 2000˜

4000 angstrom (Å

).

25. The method of claim 24, wherein said first polysilicon is formed by using chemical vapor deposition (CVD) method.

26. The method of claim 21, wherein said first type ion is P-type ion.

27. The method of claim 21, wherein said first type ion is N-type ion.

28. The method of claim 21, wherein said second type ion is P-type ion.

29. The method of claim 21, wherein said second type ion is N-type ion.

30. The method of claim 21, wherein said expitaxy base is in-situ doping polysilicon.

31. The method of claim 21, wherein said inner spacer is oxide.

32. The method of claim 21, wherein said inner spacer is NO (nitride/oxide).

35. The method of claim 21, wherein said collector region/base region/emitter region of said Bipolar Junction Transistor is P/N/P type.

36. The method of claim 21, wherein said collector region/base region/emitter region of said Bipolar Junction Transistor is N/P/N type.