Split-gate thin-film storage NVM cell

• US 20040084710A1
• Filed: 10/30/2002
• Published: 05/06/2004
• Est. Priority Date: 10/30/2002
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Prinz, Erwin J., Hoefler, Alexander, Baker, Frank K. Jr.
• Granted Patent: US 6,828,618 B2
• Time in Patent Office: Days
• US Class Current: 257/311
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor nonvolatile memory cell (30) comprising a split-gate FET device having a charge-storage transistor (38) in series with a select transistor (39). A multilayered charge-storage gate dielectric (35) extends over at least a portion of the source (32) and a first portion (341) of the channel of the FET. A select gate dielectric (36), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain (33) and a second portion (342) of the channel. A monolithic gate conductor (37) overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer (352). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a major surface;

a drain formed in the substrate;

a source formed in the substrate, the drain and the source defining a channel therebetween;

a charge-storage gate dielectric disposed on the major surface over at least a portion of the source and at least a first portion of the channel;

a select gate dielectric disposed on the major surface over at least a portion of the drain and at least a second portion of the channel so that the charge-storage gate dielectric and the select gate dielectric are contiguous; and

a gate conductor disposed over both the first gate dielectric and the charge-storage gate dielectric.

2. A semiconductor device as defined in claim 1, wherein the charge-storage gate dielectric is multilayered.

3. A semiconductor device as defined in claim 2, wherein the charge-storage gate dielectric comprises:

a bottom insulating layer;

a top insulating layer; and

an intermediate charge-storage layer.

4. A semiconductor device as defined in claim 3, wherein the bottom insulating layer is an oxide, the top insulating layer is an oxide, and the intermediate charge-storage layer is a charge-storage dielectric selected from the class comprising a nitride, silicon oxynitride, and silicon dioxide with charge-storage nanocrystals.

5. A semiconductor device as defined in claim 4, wherein the bottom insulating layer is approximately 20 to 80 angstroms in thickness and the intermediate layer is approximately 50 to 150 angstroms in thickness.

6. A semiconductor device as defined in claim 3, wherein the select gate dielectric consists essentially of a single insulating layer.

7. A semiconductor device as defined as claim 6, wherein the substrate comprises a first region subtending the charge-storage gate dielectric and a second region subtending the select gate dielectric and wherein the second substrate region is doped with a higher impurity concentration than is the first substrate region.

8. A semiconductor nonvolatile memory (NVM) cell comprising:

a semiconductor body having a top surface;

a drain formed in the semiconductor body;

a source formed in the semiconductor body and spaced apart from the drain by a predetermined distance;

a channel occupying at least a portion of the semiconductor body between the drain and the source;

a first gate dielectric disposed on the top surface of the semiconductor body and over at least a portion of the source;

a second gate dielectric disposed on the top surface of the semiconductor body and over at least a portion of the drain and juxtaposed to the first gate dielectric so that the first gate dielectric and the second gate dielectric together substantially cover an area of the channel at the top surface; and

a monolithic gate conductor covering the first gate dielectric and the second gate dielectric.

9. A semiconductor NVM cell as defined in claim 8, wherein the first gate dielectric is multilayered.

10. A semiconductor NVM cell as defined in claim 9, wherein the first gate dielectric is an ONO stack.

11. A semiconductor NVM cell as defined in claim 10, wherein the first gate dielectric and the second gate dielectric are positioned in abutment.

12. A gate structure for a nonvolatile memory (NVM) cell, the gate structure disposed over a channel and over at least respective portions of a source and a drain of the cell and comprising:

a charge-storage gate dielectric

a select gate dielectric; and

a monolithic gate conductor disposed over at least substantial portions of both the charge-storage gate dielectric and the select gate dielectric.

13. A gate structure as defined in claim 12, wherein the charge-storage gate dielectric comprises a multilayered stack consisting essentially of a bottom insulating layer, a top insulating layer, and an intermediate charge-storage layer.

14. A gate structure as defined in claim 13, wherein the charge-storage gate dielectric comprises an ONO stack.

15. A gate structure as defined in claim 14, wherein the charge-storage gate dielectric is contiguous to the select gate dielectric.

16. A gate structure as defined in claim 13, wherein the intermediate charge-storage layer is a dielectric selected from the class comprising a nitride, silicon oxynitride, and silicon dioxide with charge-storage nanocrystals.

17. A gate structure as defined in claim 16, wherein the charge-storage gate dielectric comprises an ONO stack.

18. A gate structure as defined in claim 14, wherein the ONO stack has a sidewall positioned over the channel and the select gate dielectric comprises a continuous oxide layer subtending the gate conductor and extending over a top layer of the ONO stack, alongside the sidewall, and over a portion of the channel and a portion of the drain.

19. A semiconductor nonvolatile memory (NVM) dual cell comprising:

a body consisting essentially of semiconductor material, the body having a major surface;

a first drain formed in the body of the semiconductor device;

a second drain formed in the body of the semiconductor device;

a common source formed in the body of the semiconductor device, the common source positioned laterally between the first drain and the second drain;

a first channel in the semiconductor body and defined by the first drain and the common source;

a second channel in the semiconductor body and defined by the second drain and the common source;

a first select gate dielectric disposed on the major surface over at least a portion of the first drain and at least a first portion of the first channel;

a second select gate dielectric disposed over at least a portion of the second drain and a first portion of the second channel;

a first charge-storage gate dielectric disposed over at least a portion of the common source and a second portion of the first channel, and

a second charge-storage gate dielectric disposed over at least a portion of the common source and a second portion of the second channel.

20. A semiconductor NVM dual cell as defined in claim 19, wherein each of the charge-storage gate dielectrics is multilayered.

21. A semiconductor NVM dual cell as defined in claim 20, wherein each of the charge-storage gate dielectrics comprises:

a bottom insulating layer;

a top insulating layer; and

an intermediate charge-storage layer.

22. A semiconductor NVM dual cell as defined in claim 21, wherein the bottom insulating layer is an oxide, the top insulating layer is an oxide, and the intermediate charge-storage layer is a nitride.

23. A semiconductor NVM dual cell as defined in claim 22, wherein the bottom insulating layer is approximately 20 to 80 angstroms in thickness, the top insulating layer is approximately 50 angstroms in thickness, and the intermediate charge-storage layer is approximately 50 to 150 angstroms in thickness.

24. A semiconductor NVM dual cell as defined in claim 23, wherein each of the select gate dielectrics consists essentially of a single insulating layer.

25. A method of operating a semiconductor nonvolatile memory (NVM) cell, which cell is constructed to include (i) a drain and a source formed in a semiconductor substrate;

(ii) a channel extending between the drain and the source and consisting essentially of a first channel portion proximal to the source and a second channel portion proximal to the drain;

(iii) a charge-storage gate dielectric in the form of an ONO stack disposed over at least a portion of the source and over the first channel portion and comprising a bottom insulating layer, an intermediate charge storage layer, and a top insulating layer;

(iv) a select gate dielectric consisting essentially of a single insulating layer disposed over at least a portion of the drain and over the second channel portion; and

(v) a gate conductor disposed over the charge-storage gate dielectric and the select gate dielectric;

the method comprising;

applying a programming row-select voltage to the gate conductor;

applying programming a column-select voltage to the drain; and

applying a programming bias voltage to the source so as to cause source-side hot-electron injection into the charge-storage layer of the ONO stack.

26. A method of operating a semiconductor NVM cell as defined in claim 25, further comprising:

applying an erase row-select voltage to the gate conductor;

applying a first erase bias voltage to the substrate; and

applying a second erase bias voltage to the source so as to cause source-side BTBT-induced hot-hole injection into the charge-storage layer of the ONO stack.

27. A method of operating a semiconductor NVM cell as defined in claim 25, further comprising:

applying a read row-select voltage to the gate conductor;

applying a read column-select voltage to the drain; and

applying a read bias voltage to the source so as to cause current to flow from the drain to the source of the NVM cell.

28. A fabrication process for a Split-Gate Thin-Film Storage NVM cell, the process comprising:

providing a semiconductor substrate of a first conductivity type;

successively forming a bottom insulating layer on a surface of the semiconductor substrate, an intermediate charge-storage layer on the bottom insulating layer, and a top insulating layer on the intermediate charge-storage layer;

patterning a charge-storage dielectric stack over a first portion of the semiconductor substrate;

forming a third insulating layer on the surface over a second portion of the semiconductor substrate so that the third insulating layer abuts the charge-storage dielectric stack;

depositing a monolithic gate conductor over the charge-storage dielectric stack and over the third insulating layer;

etching (i) a portion of the gate conductor and a portion of the charge-storage dielectric stack to form a first sidewall and (ii) a portion of the gate conductor and a portion of the third insulating layer to form a second sidewall; and

implanting areas of the semiconductor substrate that are respectively aligned with the first sidewall and the second sidewall with an impurity of a second conductivity type so that a source region is formed that subtends at least a portion of the charge-storage dielectric stack and so that a drain region is formed that subtends at least a portion of the third insulating layer.

29. A fabrication process for a Split-Gate Thin-Film Storage NVM Cell, as defined in claim 28, further comprising:

implanting an impurity of the first conductivity type into a second portion of the semiconductor substrate so as to establish the charge-neutral threshold voltage of a select transistor that includes the drain, the third insulating layer, the second portion of the substrate and the monolithic conductor.

30. A fabrication process for a Split-Gate Thin-Film Storage NVM cell as defined in claim 29, further comprising:

forming a first sidewall spacer on the surface of the substrate and adjacent to the first sidewall;

forming a second sidewall spacer on the surface of the substrate and adjacent to the second sidewall; and

implanting areas of the semiconductor substrate with an impurity of the second conductivity type to form an additional source region aligned with the first sidewall spacer and an additional drain region aligned with the second sidewall spacer.

31. A fabrication process for a Split-Gate Thin-Film Storage NVM Cell as defined in claim 29, wherein the bottom insulating layer is an oxide, the top insulating layer is an oxide, and the intermediate charge-storage layer is a dielectric selected from the class comprising a nitride, silicon oxynitride and silicon dioxide with nanocrystals.

32. A fabrication process for a Split-Gate Thin-Film Storage NVM Cell as defined in claim 31, further comprising:

forming a first sidewall spacer on the surface of the substrate and adjacent to the first sidewall;

forming a second sidewall spacer on the surface of the substrate and adjacent to the second sidewall; and

implanting exposed areas of the semiconductor substrate with an impurity of the second conductivity type to form an additional source region aligned with the first sidewall spacer and an additional drain region aligned with the second sidewall spacer.