Solid state imaging device and equipment using the same

• US 20040095495A1
• Filed: 09/30/2003
• Published: 05/20/2004
• Est. Priority Date: 09/30/2002
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Inokuma, Kazuyuki, Yamaguchi, Takumi, Fujii, Toshiya, Kasuga, Shigetaka
• Granted Patent: US 7,164,113 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H04N 23/54 Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils

Abstract

The present invention provides a small, high-performance imaging device and its application to products at low cost by preventing noise superimposed on a timing pulse feed line from affecting the output of an imaging chip. The imaging device includes two chips: an imaging chip 101 including a sensor 102 and an image processing chip 106 including an image processing circuit 110. The transistors of all circuits in the imaging chip 101 are formed as either nMOS or pMOS transistors. The imaging chip 101 is stacked on the image processing chip 106.

Claims

1. A solid state imaging device comprising:

an imaging semiconductor chip in which all transistors are formed of the same electric conductor; and

an image processing semiconductor chip comprising CMOS transistors.

2. The solid state imaging device according to claim 1, wherein the imaging semiconductor chip is stacked on the image processing semiconductor chip.

3. The solid state imaging device according to claim 1, wherein all transistors of the imaging semiconductor chip are formed as n-channel MOS transistors.

4. The solid state imaging device according to claim 1, wherein all transistors of the imaging semiconductor chip are formed as p-channel MOS transistors.

5. The solid state imaging device according to claim 1, wherein the imaging semiconductor chip comprises:

a photoelectric converter for converting light into an electric charge; and

an amplifier for amplifying a signal that corresponds to the electric charge generated by the photoelectric converter.

6. The solid state imaging device according to claim 1, wherein the imaging semiconductor chip and the image processing semiconductor chip are connected electrically by a bonding wire.

7. The solid state imaging device according to claim 1, wherein a through electrode is provided in the imaging semiconductor chip, and the imaging semiconductor chip and the image processing semiconductor chip are connected electrically via wiring connected to the through electrode.

8. The solid state imaging device according to claim 7, wherein the through electrode is a Si through electrode.

9. The solid state imaging device according to claim 1, wherein the image processing semiconductor chip comprises:

a timing generator for supplying a timing pulse to the imaging semiconductor chip;

a gain control amplifier; and

an analog/digital converter.

10. The solid state imaging device according to claim 2, wherein the image processing semiconductor chip comprises a plurality of terminals including a timing pulse output terminal for outputting a timing pulse,

the imaging semiconductor chip comprises a plurality of terminals including a timing pulse input terminal for receiving the timing pulse, and

the imaging semiconductor chip is stacked on the image processing semiconductor chip so that the timing pulse input terminal and the timing pulse output terminal are located close to each other.

11. The solid state imaging device according to claim 2, wherein the imaging semiconductor chip comprises a plurality of terminals including an image signal output terminal for outputting an image signal,

the image processing semiconductor chip comprises a plurality of terminals including an image signal input terminal for receiving the image signal, and

the imaging semiconductor chip is stacked on the image processing semiconductor chip so that the image signal output terminal and the image signal input terminal are located close to each other.

12. Equipment comprising:

the solid state imaging device according to claim 1;

and

an image processing portion for processing a static image or a dynamic image produced by the solid state imaging device.

13. The equipment according to claim 12, wherein the equipment is a cellular phone.

14. The equipment according to claim 12, wherein the equipment is an information terminal.

15. The equipment according to claim 12, wherein the equipment is a digital still camera.