Method of fabricating heterojunction photodiodes integrated with cmos

• US 20040097021A1
• Filed: 04/17/2003
• Published: 05/20/2004
• Est. Priority Date: 10/19/2000
• Status: Active Grant

• Current Assignee: Quantum Semiconductor LLC
• Original Assignee: Quantum Semiconductor LLC
• Inventors: Augusto, Carlos J.R.P., Forester, Lynn
• Granted Patent: US 6,943,051 B2
• Time in Patent Office: Days
• US Class Current: 438/149
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Abstract

A method in which thin-film p-i-n heterojunction photodiodes are formed by selective epitaxial growth/deposition on pre-designated active-area regions of standard CMOS devices. The thin-film p-i-n photodiodes are formed on active areas (for example n⁺-doped), and these are contacted at the bottom (substrate) side by the “well contact” corresponding to that particular active area. There is no actual potential well since that particular active area has only one type of doping. The top of each photodiode has a separate contact formed thereon. The selective epitaxial growth of the p-i-n photodiodes is modular, in the sense that there is no need to change any of the steps developed for the “pure” CMOS process flow. Since the active region is epitaxially deposited, there is the possibility of forming sharp doping profiles and band-gap engineering during the epitaxial process, thereby optimizing several device parameters for higher performance. This new type of light sensor architecture, monolithically integrated with CMOS, decouples the photo-absorption active region from the MOSFETs, hence the bias applied to the photodiode can be independent from the bias between the source, drain, gate and substrate (well) of the MOSFETs.

Claims

1. A method of fabricating a heterojunction photodiode monolithically integrated with CMOS, comprising the steps of:

(a) Fabrication of CMOS structures in which a plurality of active areas exist, some with standard CMOS processing and a few selected others where only one doping type is implanted for both well and junction, on a semiconductor substrate,

(b) Selective epitaxial growth of a photodiode module on selected ones of said plurality of active areas,

(c) Formation of a contact layer for metal interconnects on at least selected areas of each epitaxially grown photodiode module,

(d) Formation of metal interconnects on top of said contact layer.

2. The method as claimed in claim 1, wherein said contact layer for metal interconnects is an opaque conducting material, for example a metal silicide layer, formed on selected areas of each epitaxially grown photodiode module.

3. The method as claimed in claim 1, wherein said contact layer for metal interconnects is a conducting light-transparent layer deposited on top of each epitaxially grown photodiode module.

4. The method as claimed in claim 1, wherein the step of selective epitaxial growth of photodiode module comprises the steps of:

Epitaxial growth of a stack of thin silicon alloy films with a specific range of germanium and/or carbon atomic concentration on a selected active area, the germanium and/or carbon atomic concentration decreasing from the lower film to the upper film,

said upper film being of the type opposite to the type of the top layer of the active area underneath the stack.

5. The method as claimed in claim 1, wherein said epitaxially grown p-i-n photodiode is made of a stack of silicon random alloy films.

6. The method as claimed in claim 1, wherein said epitaxially grown p-i-n photodiode is made of a stack of silicon alloy quantum wells.

7. The method as claimed in claim 1, wherein said epitaxially grown p-i-n photodiode is made of a stack of silicon alloy superlattice films.

8. The method as claimed in claim 7, wherein a thin heavily doped silicon cap film is epitaxially grown on top of said stack.

9. The method as claimed in claim 1, wherein the step of selective epitaxial growth of photodiode module comprises the steps of:

Epitaxial growth of a stack of thin-films of epitaxially compatible materials such as PbTe, Pb<sub>1−

x</sub>Sn_xSe, ZnS, GaN, AlN, Al₂O₃, LaAlO₃, Pr₂O₃, CeO₂, CaF₂, Sr₂TiO₄, SrTiO₃, etc.

10. The method as claimed in claim 9, wherein said epitaxially grown p-i-n photodiode is made of a stack of PbTe, Pb₁₋

xSn_xSe, ZnS, GaN, AlN, films.

11. The method as claimed in claim 9, wherein said epitaxially grown p-i-n photodiode is made of a stack of quantum wells made with silicon and any of the epitaxially compatible materials such as PbTe, Pb₁₋

xSn_xSe, ZnS, GaN, AlN, Al₂O₃, LaAlO₃, Pr₂O₃, CeO₂, CaF₂, Sr₂TiO₄, SrTiO₃, etc.

12. The method as claimed in claim 9, wherein said epitaxially grown p-i-n photodiode is made of a stack of superlattice films made with silicon and any of the epitaxially compatible materials such as PbTe, Pb₁₋

xSn_xSe, ZnS, GaN, AlN, Al₂O₃, LaAlO₃, Pr₂O₃, CeO₂, CaF₂, Sr₂TiO₄, SrTiO₃, etc.

13. The method as claimed in either of claims 9-12, wherein said epitaxially grown p-i-n photodiode is made on a buffer film allowing strain relaxation with respect to the silicon crystalline lattice.

16. An optical to electronic transceiver comprising CMOS circuitry monolithically integrated with light-sensing devices fabricated according to the method of claim 1.

14. A CMOS imager sensor including a common semiconductor substrate and a plurality of side-by-side spaced apart integrated light-sensing devices arranged for sensing light on a face of said substrate, said plurality of light-sensing devices including light-sensing devices adapted for sensing each a specific range of wavelengths in the visible, and/or infra-red, and/or ultra-violet spectrum.

15. The CMOS imager sensor as claimed in claim 14, further including light-sensing areas operating as solar cells for power generation.