Reconfigurable programmable logic device computer system

• US 20040098569A1
• Filed: 09/19/2003
• Published: 05/20/2004
• Est. Priority Date: 11/20/1998
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Southgate, Timothy J., Smith, Stephen J.
• Granted Patent: US 7,171,548 B2
• Time in Patent Office: Days
• US Class Current: 712/229
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system.

Claims

1. A reconfigurable computer system comprising:

a central processing unit implemented on at least one programmable logic device; and

programmable logic coupled to the central processing unit that is reconfigurable to optimize the ability of the computer system to handle a given application.

2. The reconfigurable computer system defined in claim 1 further comprising non-volatile memory coupled to the programmable logic, wherein the non-volatile memory stores initial configuration data that is used by the programmable logic during a boot phase.

3. The reconfigurable computer system defined in claim 1 further comprising random-access memory coupled to the programmable logic, wherein the random access memory stores data and state information.

4. The reconfigurable computer system defined in claim 1 further comprising input-output circuitry implemented in programmable logic, wherein the input-output circuitry is coupled to the central processing unit and the programmable logic.

5. A reconfigurable computer system comprising:

programmable logic that is reconfigurable to optimize the ability of the computer system to run a given application, wherein the programmable logic is adapted to accommodate installation of additional programmable logic, and wherein there is an increase in performance when running the application whenever such additional programmable logic is installed without recompiling the application.

6. A method for using software development tools to develop software for a reconfigurable computer that contains programmable logic resources that are reconfigurable to optimize the ability of the computer to handle a given application, comprising:

using a system design language to generate hardware functions and software functions for the application; and

partitioning the application into software functions and into hardware functions that exist simultaneously during run-time.

7. The method defined in claim 6 wherein the reconfigurable computer includes a central processing unit implemented on at least one programmable logic device and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

8. The method defined in claim 6 wherein the reconfigurable computer includes a central processing unit implemented on a microprocessor and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

9. The method defined in claim 6 wherein the reconfigurable computer includes a central processing unit that is partially implemented on a microprocessor and that is partially implemented on a programmable logic device and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

10. The method defined in claim 6 further comprising using a resource library to provide information to a partitioner on properties of the programmable logic resources.

11. The method defined in claim 6 further comprising using a resource library to provide information to a partitioner on properties of the central processing unit and on properties of memory in the reconfigurable computer.

12. The method defined in claim 6 further comprising generating hardware functions that are written and compiled based on a unit hardware abstraction.

13. The method defined in claim 6 further comprising partitioning the hardware functions and the software functions automatically using a partitioner.

14. The method defined in claim 6 further comprising partitioning the hardware functions and the software function manually.

15. A method for managing resources in a reconfigurable computer that contains programmable logic resources that are reconfigurable to optimize the ability of the computer to handle a given application comprising:

managing programmable logic resource allocation with a virtual logic manager.

16. The method defined in claim 15 wherein the reconfigurable computer includes a central processing unit implemented on at least one programmable logic device and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

17. The method defined in claim 15 wherein the reconfigurable computer includes a central processing unit implemented on a microprocessor and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

18. The method defined in claim 15 wherein the reconfigurable computer includes a central processing unit that is partially implemented on a microprocessor and that is partially implemented on a programmable logic device and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

19. The method defined in claim 15 further comprising swapping configuration data between a secondary storage device and the programmable logic resources during programmable logic resource allocation using the virtual logic manager.

20. A method for managing resources in a computer that contains programmable logic resources that are reconfigurable to optimize the ability of the computer to handle a given application having multiple functions comprising:

using a virtual computer operating system to determine whether there are sufficient programmable logic resources available to be reconfigured to perform a given one of the functions of the application;

using the virtual computer operating system to measure the performance of the application at run-time and to compare the measured performance to specified performance requirements;

using the virtual computer operating system to allocate the programmable logic resources among the multiple functions of the application based on the comparison of the measured performance to the specified performance requirements; and

using the virtual computer operating system to determine whether a hardware implementation or a software implementation is to be used for the given function based on the comparison of the measured performance to the specified performance requirements.

21. The method defined in claim 20 wherein the reconfigurable computer includes a central processing unit implemented on at least one programmable logic device and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

22. The method defined in claim 20 wherein the reconfigurable computer includes a central processing unit implemented on a microprocessor and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

23. The method defined in claim 20 wherein the reconfigurable computer includes a central processing unit that is partially implemented on a microprocessor and that is partially implemented on a programmable logic device and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

24. The method defined in claim 20 wherein the application includes multiple functions, the method further comprising allocating a single one of the programmable logic resources to a plurality of blocks of configuration data that make up a given function.

25. The method defined in claim 20 wherein the application includes multiple functions, the method further comprising allocating a single one of the programmable logic resources to a single block of configuration data that makes up a given function.

26. The method defined in claim 20 wherein the virtual computer operating system resides on a system that uses virtual logic.

27. The method defined in claim 20 wherein the virtual computer operating system resides on a system that does not use virtual logic.