CMOS imager with selectively silicided gate
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Abstract
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.
35 Citations
128 Claims
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1. - 16. (Canceled)
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17. ( A method of forming a CMOS imager, comprising the steps of:
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forming an insulating layer over a semiconductor substrate having a photo-collection region;
forming at least one transistor gate over a portion of said insulating layer;
forming an opaque conductive layer over said photocollection region, said at least one transistor gate and said insulating layer; and
selectively removing said opaque conductive layer from said insulating layer and said photocollection region. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 39, 40, 41, 42, 43)
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38. (T ) The method according to daim 28, wherein said opaque conductive layer silicide layer is deposited by sputtering.
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44. A method of forming a CMOS imager, comprising the steps of:
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forming an insulating layer over a semiconductor substrate having a doped photocollection region;
depositing a doped polysilicon layer over said insulating layer;
depositing a photocollection insulator over said photocollection region;
forming an opaque conductive layer over said doped polysilicon layer; and
patterning said imager to form at least one gate stack having said opaque conductive layer over said gate stack. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70)
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71. - 86. (Canceled)
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87. (P A CMOS imager having improved transistor speed comprising:
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a substrate doped to a first conductivity type;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array. - View Dependent Claims (88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101)
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102. (I A processing system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor and including;
a substrate doped to a first conductivity type;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array. - View Dependent Claims (103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116)
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117. 1 A CMOS imager having improved transistor speed comprising:
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a substrate doped to a first conductivity type;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array, wherein said photogate is void of said deposited opaque conductive layer.
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118. 9A processing system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor and including;
a substrate doped to a first conductivity type;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array, wherein said photogate is void of said deposited opaque conductive layer.
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119. ) A CMOS imager having improved transistor speed comprising:
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a substrate; and
an array of pixel cells formed on said substrate, each of said cells including a photogate, a transfer gate, a reset gate, and a partially removed opaque conductive layer, wherein a remaining portion of said opaque conductive layer remains over said transfer gate and said reset gate, and wherein said photogate is void of said opaque conductive layer. - View Dependent Claims (120, 121, 122, 123, 124, 125, 126, 127, 128)
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Specification
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Current AssigneeRound Rock Research LLC
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Original AssigneeHoward E. Rhodes
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InventorsRhodes, Howard E.
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current257/292
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CPC Class CodesH01L 27/14603 Special geometry or disposi...H01L 27/14609 Pixel-elements with integra...H01L 27/1462 CoatingsH01L 27/14623 Optical shieldingH01L 27/14643 Photodiode arrays; MOS imagersH01L 27/14687 Wafer level processingH01L 27/14689 MOS based technologies
