Method and apparatus for pausing execution in a processor or the like

• US 20040117604A1
• Filed: 12/08/2003
• Published: 06/17/2004
• Est. Priority Date: 01/21/2000
• Status: Active Grant

• Current Assignee: Deborah T. Marr, Dion Rodgers
• Original Assignee: Deborah T. Marr, Dion Rodgers
• Inventors: Rodgers, Dion, Marr, Deborah T.
• Granted Patent: US 7,451,296 B2
• Time in Patent Office: Days
• US Class Current: 712/226
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets a Bit flag in memory indicating that execution for the thread has been paused. The SET instruction is placed in the pipeline for execution. The following READ instruction for that thread, however, is prevented from entering the pipeline until, the SET instruction is executed and retired (resulting in a clearing of the Bit flag). Once the Bit flag has been cleared, the READ instruction is placed in the pipeline for execution. During the time that processing of one thread is paused, the execution of other threads may continue.

Claims

1. A method of pausing execution of instructions in a thread, comprising:

determining if a next instruction for a first thread is an instruction of a first type; and

preventing instructions of said first thread from being processed for execution for a period of time while instructions from a second thread can be processed for execution.

2. The method of claim 1 wherein said next instruction of a first type is a SET instruction and a following instruction is a READ instruction

3. The method of claim 2 wherein said SET instruction causes a value to be stored in memory for said first thread.

4. The method of claim 3 further comprising:

processing said READ instruction for execution when said value stored in memory is reset.

5. The method of claim 4 wherein said value stored in memory is reset when said SET instruction is retired.

6. A method of pausing execution of instructions in a thread, comprising:

determining if a next instruction for a first thread is an instruction of a first type;

initiating a counter; and

preventing instructions of said first thread from being processed for execution until said counter reaches a predetermined value.

7. The method of claim 6 wherein said instruction includes an operand and said initiating step includes loading said counter with said operand.

8. The method of claim 6 wherein instructions for a second thread can be processed for execution while instructions of said first thread are prevented from being processed.

9. A method of reducing power consumption in a processor system comprising:

receiving a pause instruction from a first thread at a decode unit in said processor system;

preventing instructions of said first thread from being processed for execution for a period of time while instructions from a second thread can be processed for execution.

10. The method of claim 9 wherein execution of software code causes said pause instruction to be received at said decode unit.

11. An apparatus pausing execution of instructions in a thread, comprising:

a decode unit to determine if a next instruction for a first thread is an instruction of a first type, said decode unit to prevent instructions of said first thread from being processed for execution for a period of time while instructions from a second thread can be processed for execution.

12. The apparatus of claim 11 wherein said next instruction of a first type is a SET instruction and a following instruction is a READ instruction

13. The apparatus of claim 12 further comprising:

a memory, wherein said SET instruction causes a value to be stored in memory for said first thread.

14. The apparatus of claim 13 wherein said decode unit processes said READ instruction for execution when said value stored in memory is reset.

15. The apparatus of claim 14 further comprising:

a retire unit coupled to said decode unit wherein said retire unit causes said value stored in memory to be reset when said SET instruction is retired by said retire unit.

16. An apparatus for pausing execution of instructions in a thread, comprising:

a decode unit to determine if a next instruction for a first thread is an instruction of a first type;

a counter that is initiated when said next instruction for a first thread is an instruction of a first type, said decode unit to prevent instructions of said first thread from being processed for execution until said counter reaches a predetermined value.

17. The apparatus of claim 16 wherein said instruction includes an operand to be loaded into said counter.

18. The apparatus of claim 16 wherein instructions for a second thread can be processed for execution while instructions of said first thread are prevented from being processed.

19. An apparatus for reducing power consumption in a processor system comprising:

a processor system including

a decode unit to receive a pause instruction from a first thread in said processor system, said decode unit to prevent instructions of said first thread from being processed for execution for a period of time while instructions from a second thread can be processed for execution.

20. The apparatus of claim 19 wherein execution of software code at said processor system causes said pause instruction to be received at said decode unit.