Single ended clock signal generator having a differential output

• US 20040119509A1
• Filed: 12/20/2002
• Published: 06/24/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Akyildiz, Ahmet, Shkidt, Alex, Richmond, Greg
• Granted Patent: US 6,836,169 B2
• Time in Patent Office: Days
• US Class Current: 327/100
• CPC Class Codes: H03K 5/151 with two complementary outputs

Abstract

Embodiments of the present invention provide for generating a sampled differential pattern signal with reduced jitter. In one embodiment of the present invention, a seed frequency generator provides a differential seed frequency signal. The differential seed frequency signal is converted to a single ended seed frequency signal by a differential-to-single ended converter. The pattern generation logic utilizes the single end seed frequency signal to generate single ended pattern signals. Single ended-to-differential samplers then generate a sampled differential pattern signal by sampling the single ended pattern signal according to the differential seed frequency signal.

Claims

1. A pattern generator comprising:

a pattern generation -logic generating a single ended pattern signal from a single ended seed frequency signal; and

a single-to-differential sampler coupled to said pattern generation logic and generating a sampled differential pattern signal based on said single ended pattern signal, wherein said single-to-differential sampler is clocked by a differential clock signal.

2. The pattern generator according to claim 1, further comprising a converter coupled to said pattern generation logic for converting a differential seed frequency signal to said single ended seed frequency signal.

3. The pattern generator according to claim 2, further comprising a seed frequency generator coupled to said converter and for providing said differential seed frequency signal.

4. The pattern generator according to claim 3, wherein said pattern generation logic is a low power circuit and wherein said differential seed frequency signal is generated by said seed frequency generator.

5. The pattern generator according to claim 1, wherein noise present on said single ended pattern signal is reduced in said sampled differential pattern signal.

6. The pattern generator according to claim 1, wherein said sampled differential pattern signal generated by said single-to-differential sampler is substantially jitter free.

7. The pattern generator according to claim 1, wherein said pattern generation logic reduces fabrication area occupied by said pattern generator.

14. The pattern generator according to claim 1, further comprising:

a latch couple to said sampled differential pattern signal and generating a latched sampled differential pattern signal, wherein said latch is latched by said differential clock signal;

an or-gate coupled to said sampled differential pattern and said latched sampled differential pattern signal and generating a fifty percent duty cycle sampled differential pattern signal.

8. A pattern generator comprising:

a single ended pattern generation logic generating a single ended pattern signal from a single ended seed frequency signal; and

a differential flip-flop coupled to said single ended pattern generation logic, wherein a sampled differential pattern signal is generated by said differential flip-flop by sampling said single ended pattern signal according to a differential seed frequency signal.

9. The pattern generator according to claim 8, further comprising a re-synchronization flip-flop coupled between said single ended pattern generation logic and said differential flip-flop, wherein said single ended pattern signal is re-synchronized by said re-synchronization flip-flop to said single ended seed frequency signal.

10. The pattern generator according to claim 8, further comprising a complimentary flip-flop coupled between said single ended pattern generation logic and said differential flip-flop, wherein said single ended pattern signal is converted by said complimentary flip-flop to a complimentary single ended clock signal.

11. The pattern generator according to claim 8, further comprising a phase lock loop voltage controlled oscillator coupled to said single ended pattern generation logic.

12. The pattern generator according to claim 11, further comprising a converter coupled between said phase lock loop voltage controlled oscillator and said single ended pattern generation logic, wherein a differential seed frequency signal is converted by said converter to said single ended seed frequency signal and wherein said phase lock loop voltage controlled oscillator also generates said differential seed frequency signal.

13. The pattern generator according to claim 8, wherein jitter on said sampled differential pattern signal is reduced.

15. The pattern generator according to claim 8, further comprising a second converter, wherein said sampled differential pattern signal is converted by said second converter to a sampled single ended pattern signal.

16. A method of generating a reduced jitter signal comprising:

generating a single ended pattern signal from a single ended seed frequency signal; and

converting said single ended pattern signal to a sampled differential pattern signal wherein said step of converting is based on a differential seed frequency signal.

17. The method of claim 16, wherein said single ended pattern signal is sampled at a transition crossing of a differential seed frequency signal from which said single ended seed frequency signal is generated.

18. The method of claim 17, further comprising converting said differential seed frequency signal to said single ended seed frequency signal.

19. The method of claim 18, further comprising generating said differential seed frequency signal.

20. The method of claim 16, wherein jitter present on said single ended pattern signal is reduced in said sampled differential pattern signal by sampling based upon said single ended seed frequency.