System and method for divisor threshold control in a modulation domain divider

• US 20040119624A1
• Filed: 12/10/2003
• Published: 06/24/2004
• Est. Priority Date: 12/23/2002
• Status: Active Grant

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Karlquist, Richard K.
• Granted Patent: US 6,781,534 B2
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: G06G 7/16 for multiplication or division G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00

Abstract

A modulation domain divider is disclosed that causes the divider output to be attenuated when the divisor input falls below the divisor threshold. Attenuation is accomplished by implementing the divider in the modulation domain and substituting an unmodulated signal for the normal modulated signal when the divisor is below the threshold value.

Claims

1. A circuit for providing an output signal that is the ratio of two input signals, said circuit comprising:

a phase modulator for providing a quotient signal having a phase modulation index proportional to the ratio of a dividend input signal to a divisor input signal; and

a phase attenuator for attenuating the phase modulation index of said quotient signal when said divisor is below a divisor threshold.

2. The circuit of claim 1 wherein said phase modulation index approaches zero as said divisor signal approaches zero.

3. The circuit of claim 1 wherein said phase attenuator comprises:

an adder for combining a substitute carrier signal with said quotient signal.

4. The circuit of claim 3 wherein said substitute carrier signal is an unmodulated signal.

5. The circuit of claim 3 wherein said phase modulation index is controlled by the modulation value of said substitute carrier signal when said divisor is below said divisor threshold.

6. The circuit of claim 3 further comprising:

a vector modulator having adjustable I and Q DC input signals, said vector modulator operable for controlling the phase and amplitude of said substitute carrier.

7. The circuit of claim 1 further comprising:

a phase demodulator for phase demodulating said quotient signal to provide an output signal as a baseband signal.

8. The circuit of claim 1 wherein said phase modulator is an Armstrong phase modulator modified to have its modulation sensitivity controllable.

9. The circuit of claim 1 wherein said quotient signal includes amplitude modulation and wherein said circuit further includes:

a limiter for removing any said amplitude modulation from said quotient signal.

10. The circuit of claim 1 wherein said phase attenuator comprises:

an adder for adding an unmodulated substitute carrier signal to said quotient signal; and

a limiter inserted ahead of said adder.

11. The circuit of claim 10 wherein said limiter operates linearly for signals below said divisor threshold value and operates to clip signals above said divisor threshold value.

12. The circuit of claim 1 wherein said limiter operates exponentially for signals below said divisor threshold and operates to clip signals above said divisor threshold.

13. An Armstrong modulator having a dividend input and a divisor input and a carrier injection signal, said modulator comprising:

means for modifying the operation of said modulation so as to enable a signal on said divisor input to maintain inverse proportional control of the modulation gain of said modulator; and

means for further modifying said operation of said modulation so as to control an output signal in accordance with an unmodulated substitute carrier signal when said signal on said divisor input is below a certain value.

14. The Armstrong modulator of claim 13 wherein said divisor input certain value is set, at least in part, by the amplitude of said unmodulated substitute carrier signal.

15. A method for providing a division function in the modulation domain, said method comprising:

modifying an Armstrong phase modulator to enable the divisor signal to maintain inverse proportional control of the modulation gain of said Armstrong phase modulator by varying the carrier injection signal level; and

reducing said modulation gain when said divisor signal is below a preestablished divisor threshold.

16. The method of claim 15 wherein as the value of said divisor signal approaches zero, said modulator gain approaches zero.

17. The method of claim 15 wherein said reducing comprises:

injecting an unmodulated substitute carrier signal such that said divisor threshold is set by the amplitude of said injected unmodulated substitute carrier signal.

18. A circuit for dividing a first analog signal by a second analog signal, said circuit comprising:

a double side band suppressed carrier modulator for accepting said first analog signal and for accepting a sine wave carrier signal;

an amplitude modulator for accepting said second analog signal and for accepting a phase shifted carrier signal;

a first adder for combining the outputs of said double side band suppressed carrier modulator and said amplitude modulator;

a first limiter for removing at least a portion of the amplitude modulation of the signal output from said first adder;

a second adder for combining the output of said first limiter with an unmodulated substitute carrier signal; and

a phase demodulator for accepting said carrier signal and for accepting the output of said second adder, said phase demodulator providing, as an output, a signal which is either said first signal divided by said second signal when said divisor is above a divisor threshold value or an attenuated version of the signal consisting of said first signal divided by said second signal when said divisor is below said divisor threshold value.

19. The circuit of claim 18 wherein said attenuated version of said signal approaches zero as said second signal approaches zero.

20. The circuit of claim 18 wherein said attenuated signal is controlled, at least in part, by an unmodulated carrier injection signal.

21. The circuit of claim 18 wherein at least one of said double side-band suppressed carrier modulator, said amplitude modulator and said phase modulator is a multiplier circuit.

22. The circuit of claim 18 further including:

a second limiter for accepting the output from said second adder prior to said output being supplied to said phase modulator.

23. A method of processing a pair of input signals, said method comprising:

adding together a first signal comprised of a first one of said input signals modulated by a sine wave carrier and a second signal comprised of said second one of said input signals modulated by a cosine wave carrier;

comparing the output of said added together signals with an unmodulated signal having a magnitude equal to the magnitude of said added together signals when the second signal is at a predetermined threshold value, and a phase equal to said added together signals, so as to provide said output if said added together signals when said second signal is above said threshold value and to provide a signal with attenuated modulation when said second signal is below said threshold value; and

phase demodulating the output of either of said provided signals.

24. The method of claim 23 further comprising:

limiting the amplitude modulation after said adding step.

25. The method of claim 23 further comprising:

limiting the output after said comparing.

26. A method of processing a pair of input signals, said method comprising:

modulating a carrier signal by a first one of said input signals;

modulating a phase shifted carrier signal by a second one of said input signals;

adding together said first and second modulated signals;

combining together an amplitude limited output signal from said added together first and second modulated signals with an unmodulated carrier signal to provide said amplitude limited output signal when the amplitude of said unmodulated carrier signal is equal to or less than the amplitude of said amplitude limited output signal and to provide an output signal with reduced modulation when the amplitude of said unmodulated carrier signal is greater than the amplitude of said amplitude limited output signal; and

phase demodulating the output of said combining step.

27. The method of claim 26 wherein said default output signal is controlled by the phase of said unmodulated carrier signal.

28. The method of claim 26 further comprising:

clipping the amplitude of the signal from said added together first and second modulated signals when the amplitude of said unmodulated carrier signal is greater than the amplitude of said signal from said added together first and second modulated signals.

29. A circuit for processing input signals;

said circuit comprising;

a first multiplier having one input for accepting one of said input signals and a second input for accepting a sine wave carrier signal;

a second multiplier having one input for accepting a second one of said input signals and a second input for accepting a signal that has been phase shifted from said sine wave carrier;

a first adder for adding the outputs of said multipliers to provide an added output signal;

a limiter for removing amplitude modulation from said added output signal;

a second adder for adding the output of said limiter with an unmodulated carrier signal derived by attenuating said signal that has been phase shifted from said sine wave carrier, said adder operating such that the modulation on its output signal is attenuated when the amplitude of said unmodulated carrier signal is greater than the amplitude of said limiter output signal, and its output signal has the same phase as said limiter output signal when the amplitude of said unmodulated carrier signal is less than the amplitude of said limiter output signal; and

a third multiplier having one input for accepting said second adder output signal, a second input for accepting said sine wave carrier signal so as to provide an output signal that is the quotient of said first signal divided by said second signal when the amplitude of said unmodulated substitute carrier signal is greater than the amplitude of said limiter output signal.

30. The circuit of claim 29 further comprising:

a limiter for stripping off at least a portion of the amplitude modulation of the output from said second adder prior to said signal being presented to said third modulator.

31. A method of processing a pair of input signals, said method comprising:

modulating a carrier signal by a first one of said input signals;

phase shifting a modulation domain second input signal;

adding together said first input modulated signal and said phase shifted second input signal to provide a quotient output signal as a modulated output signal; and

at least partially replacing said quotient output signal with an unmodulated signal when said second input signal is less than a certain value.

32. The method of claim 31 further comprising:

fully replacing said quotient signal with said unmodulated signal when said second input signal is zero.

33. The method of claim 31 further comprising:

setting said certain value by adjusting the magnitude of said unmodulated signal.