Digital display driving circuit for light emitting diode display

• US 20040119667A1
• Filed: 05/13/2003
• Published: 06/24/2004
• Est. Priority Date: 01/22/1999
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Yang, Chien-Sheng
• Granted Patent: US 7,109,957 B2
• Time in Patent Office: Days
• US Class Current: 345/82
• CPC Class Codes: G06F 3/1431 using a single graphics controller
• CPC Class Codes: G06F 3/1475 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 5/366 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory

Abstract

A digital display driving circuit is provided for driving a light emitting diode (LED) display to generate video images. The digital display driving circuit comprises a digital gamma-correction circuit for performing a digital gamma-correction process on the digitized video data to produce the desired video signals. An LED timing control circuit is applied for converting a plurality of timing signals into an LED timing control signal. And a PWM and shutdown circuit is applied for supplying power to the LED display and shutting down the LED display when the LED display has been idle for a preset period.

Claims

1. A digital display driving circuit of light emitting diode (LED) displays for driving LED displays to display video images, comprising:

a digital gamma-correction circuit, coupled to directly receive digitized displaying data from a display memory unit, for performing a digital gamma-correction process on the digitized displaying data to produce video signals;

an LED timing control circuit, coupled separately with an external time control circuit and said digital gamma-correction circuit, for converting a plurality of timing signals into an LED timing control signal; and

a PWM and shutdown circuit for supplying power to the LED display and shutting down the LED display when the LED display has been idle for a preset period.

2. The digital display driving circuit of claim 1, wherein said digital gamma-correction circuit is coupled to a central process unit (CPU) so as to fetch the digitized displaying data directly via said CPU.

3. The digital display driving circuit of claim 1, wherein said digital gamma-correction circuit is coupled to said display memory unit in which the digitized displaying data are stored, so as to fetch the digitized displaying data directly from said display memory unit.

4. The digital display driving circuit of claim 1, wherein said plurality of timing signals received by said LED timing control circuit include a horizontal synchronizing signal, a vertical synchronizing signal and a pixel clock signal.

5. The digital display driving circuit of claim 1, wherein said LED timing control circuit comprises a means for setting a user-desired resolution for the LED display to display the video image based on a logic signal representative of the user-set resolution.

6. The digital display driving circuit of claim 1, wherein said PWM and shutdown circuit is used in conjunction with a filtering circuit to convert an input DC voltage to the power required to drive the LED display, and said PWM and shutdown circuit shuts down the LED display in response to a shutdown trigger signal.

7. An digital display driving circuit for driving a digital display panel to display a video image, comprising:

a digital gamma-correction circuit, coupled to directly receive digitized displaying data from a display memory unit, for performing a digital gamma-correction process on the digitized displaying data to produce video signals; and

a timing control circuit, coupled separately with an external time control circuit and said digital gamma-correction circuit, for converting a plurality of timing signals into an timing control signal for the digital display panel.

8. The digital display driving circuit of claim 7, wherein said digital gamma-correction circuit is coupled to said display memory unit in which the digitized displaying data are stored, so as to fetch the digitized displaying data directly from said display memory unit.

9. The digital display driving circuit of claim 7, wherein said digital gamma-correction circuit is coupled to a CPU so as to fetch the digitized displaying data directly via said CPU.

10. The digital display driving circuit of claim 7, wherein said plurality of timing signals received by said timing control circuit include a horizontal synchronizing signal, a vertical synchronizing signal and a pixel clock signal.

11. The digital display driving circuit of claim 7, wherein said timing control circuit comprises a means for setting a user-desired resolution for the digital display panel to display the video image based on a logic signal representative of the user-set resolution.

12. A displaying system, comprising a first driving circuit for driving a CRT TV to display video images and a second driving circuit for driving an LED display to display video images, wherein said first driving circuit comprises a digital encoder for processing the output signals of a first timing control circuit and digitized displaying data stored in a display memory unit to thereby generate first video signals for the CRT TV, and said second driving circuit comprises

a digital gamma-correction circuit, coupled to directly receive the digitized displaying data from said display memory unit, for performing a digital gamma-correction process on the digitized displaying data to produce second video signals for the LED display;

a second timing control circuit, coupled separately with said first timing control circuit and said digital gamma-correction circuit, for converting a plurality of timing signals into an LED timing control signal; and

a PWM and shutdown circuit for supplying power to the LED display and shutting down the LED display when the LED display has been idle for a preset period.

13. The displaying system of claim 12, wherein said digital gamma-correction circuit is coupled to said CPU so as to fetch the digitized displaying data directly from said CPU.

14. The displaying system of claim 12, wherein said digital gamma-correction circuit is coupled to said display memory unit in which the digitized displaying data are stored, so as to fetch the digitized displaying data directly from said display memory unit.

15. The displaying system of claim 12, wherein said plurality of timing signals received by said second timing control circuit include a horizontal synchronizing signal, a vertical synchronizing signal and a pixel clock signal.

16. The displaying system of claim 12, wherein said second timing control circuit comprises a means for setting a user-desired resolution for the LED display to display the video image based on a logic signal representative of the user-set resolution.

17. The displaying system of claim 12, wherein said PWM and shutdown circuit is used in conjunction with a filtering circuit to convert an input DC voltage to the power required to drive the LED display, and said PWM and shutdown circuit shuts down the LED display in response to a shutdown trigger signal.