System and method for programming hyper transport routing tables on multiprocessor systems

• US 20040122973A1
• Filed: 12/19/2002
• Published: 06/24/2004
• Est. Priority Date: 12/19/2002
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Keck, David A., Devriendt, Paul
• Application Number:
  US10/326,425
• Publication Number:
  US 20040122973A1
• Time in Patent Office: Days
• US Class Current: 709/238
• CPC Class Codes: H04L 41/0659 by isolating or reconfiguring faulty entities
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/0811 by checking connectivity
• CPC Class Codes: H04L 43/0817 by checking functioning
• CPC Class Codes: H04L 43/10 Active monitoring, e.g. heartbeat, ping or trace-route

Abstract

In some embodiments, present invention describes a system and method of dynamically programming HT tables in multiprocessor systems. HT tables are dynamically reprogrammed to modify the topology of the multiprocessor system for fault adjustment, diagnostic, performance analysis, processor hot plugging and the like. HT links can be isolated by reconfiguring the HT tables which allows diagnostics on the isolated HT links. HT links can be reconfigured to route packet traffic on certain links which allows the performance measurement for the HT links. HT tables can be reconfigure to isolate a processor so that the processor can be replaced without taking the entire system down.

Claims

1. A method in connection with multiprocessor system comprising:

at least, partially stalling execution of one or more system activities; and

dynamically modifying one or more routing tables on one or more processors, wherein each one of the routing tables representing routing destination for an incoming data packet.

2. The method of claim 1, wherein the routing destination is the one or more processors.

3. The method of claim 1, further comprising:

using the modified routing tables to direct forwarding of the incoming packet to at least one predetermined outgoing link in the multiprocessor system.

4. The method of claim 1, further comprising:

stalling the system activities after completion of any pending operation.

5. The method of claim 1, further comprising:

identifying at least one substitute memory;

transferring data from a first memory to the substitute memory; and

updating a memory mapping.

6. The method of claim 5, further comprising:

identifying at least one substitute input/output link;

transferring input/output data to the substitute input/output link; and

updating a input/output map.

7. The method of claim 6 further comprising:

disabling a first processor coupled to the first memory; and

replacing the first processor.

8. The method of claim 7, wherein the disabling the first processor includes one or more of suspending all processes running on the first processor and removing power from the first processor.

9. The method of claim 1, further comprising:

resuming the execution of the one or more system activities.

10. The method of claim 9, further comprising;

identifying at least one link for testing; and

testing the identified link.

11. The method of claim 10, wherein the testing is performed for one or more of diagnostic, fault adjustment, maintenance and performance measurement.

12. The method of claim 10, further comprising:

stalling the one or more system activities;

restoring the one or more routing tables on the one or more processors; and

resuming the execution of the one or more system activities.

13. The method of claim 12, wherein the restoring the routing tables include modifying the routing tables based on results of the testing.

14. An apparatus comprising:

a plurality of processors; and

one or more storage units coupled to each one of the processors, wherein each one of the processors is coupled via at least one hyper transport link and each at least one processor includes one or more routing tables representing routing destination for an incoming data packet and the processor is configured to dynamically modify the routing tables.

15. The apparatus of claim 14, wherein the transaction between the processors and the storage elements are coherent.

16. The apparatus of claim 14, further comprising:

at least one input-output controller coupled to at least one processor and configured to provide access to at least one peripheral device.

17. A computer program product, stored on at least one computer readable medium and comprising a set of instructions, the set of instructions is configured to

at least, partially stall execution of one or more system activities;

and

dynamically modify one or more routing tables on one or more processors, wherein each one of the routing tables representing routing destination for an incoming data packet.

18. The computer program product of claim 17, wherein the routing destination is the one or more processors.

19. The computer program product of claim 17, wherein the modified routing tables direct forwarding the incoming packet to at least one predetermined outgoing link in the multiprocessor system.

20. The computer program product of claim 17, wherein the system activities are stalled after completion of any existing operation.

21. The computer program product of claim 17, further wherein the set of instructions is further configured to:

identify at least one substitute memory;

transfer data from a first memory to the substitute memory; and

update a memory mapping.

22. The computer program product of claim 21, further wherein the set of instructions is further configured to:

identify at least one substitute input/output link;

transfer input/output data to the substitute input/output link; and

update a input/output map.

23. The computer program product of claim 22 further wherein the set of instructions is further configured to:

disable a first processor coupled to the first memory; and

replace the first processor.

24. The computer program product of claim 23, wherein the disabling the first processor includes one or more of suspending all processes running on the first processor and removing power from the first processor.

25. The computer program product of claim 17, further wherein the set of instructions is further configured to:

resume the execution of the one or more system activities.

26. The computer program product of claim 25, further wherein the set of instructions is further configured to;

identify at least one link for testing; and

test the identified link.

27. The computer program product of claim 26, wherein the testing is performed for one or more of diagnostic, fault adjustment, maintenance and performance measurement.

28. The computer program product of claim 26, further wherein the set of instructions is further configured to:

stall the one or more system activities;

restore the one or more routing tables on the one or more processors; and

resume the execution of the one or more system activities.

29. The computer program product of claim 28, wherein the restoring the routing tables include modifying the routing tables based on results of the testing.

30. An apparatus comprising:

means for at least, partially stalling execution of one or more system activities; and

means for dynamically modifying one or more routing tables on one or more processors, wherein each one of the routing tables representing routing destination for an incoming data packet.

31. The apparatus of claim 30, wherein the routing destination is the one or more processors.

32. The apparatus of claim 30, further comprising:

means for identifying at least one substitute memory;

means for transferring data from a first memory to the substitute memory; and

means for updating a memory mapping.

33. The apparatus of claim 30, further comprising:

means for identifying at least one substitute input/output link;

means for transferring input/output data to the substitute input/output link; and

means for updating a input/output map.

34. The apparatus of claim 30 further comprising:

means for disabling a first processor coupled to the first memory; and

means for replacing the first processor.

35. The apparatus of claim 30, further comprising:

means for resuming the execution of the one or more system activities.

36. The apparatus of claim 35, further comprising;

means for identifying at least one link for testing; and

means for testing the identified link.

37. The apparatus of claim 36, further comprising:

means for stalling the one or more system activities;

means for restoring the one or more routing tables on the one or more processors; and

means for resuming the execution of the one or more system activities.