Reconfigurable digital processing system for space
First Claim
1. A method for the repair of an electronics payload for a space vehicle unreachable for manned repair intervention, comprising the steps of:
- providing an electronics payload including a field programmable gate array processor;
initially configuring the gate array processor for a predetermined task;
detecting when the field programmable gate array processor is not operating properly; and
, reconfiguring the non-operational field programmable gate array processor, whereby a configuration change may be uploaded to the space vehicle for the repair of the electronics payload.
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Accused Products
Abstract
A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor. In one embodiment, multiple FPGAs are connected together by a data bus and are also provided with data pipes which interconnect selected FPGAs together to provide the necessary processing function. Flexibility in reconfiguration includes the utilizing of a timing and synchronization block as well as a common configuration block which when coupled to an interconnect block permits reconfiguration of a customizable application core, depending on the particular signal processing function desired. The result is that damaged or inoperable signal processing components can be repaired in space without having to physically attend to the hardware by transmitting to the spacecraft commands which reconfigure the particular FPGAs thus to alter their signal processing function. Also mission changes can be accomplished by reprogramming the FPGAs.
26 Citations
20 Claims
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1. A method for the repair of an electronics payload for a space vehicle unreachable for manned repair intervention, comprising the steps of:
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providing an electronics payload including a field programmable gate array processor;
initially configuring the gate array processor for a predetermined task;
detecting when the field programmable gate array processor is not operating properly; and
,reconfiguring the non-operational field programmable gate array processor, whereby a configuration change may be uploaded to the space vehicle for the repair of the electronics payload. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for accommodating a change in mission for a space vehicle, comprising the steps of:
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providing the space vehicle with a field programmable gate array for performing a signal processing function for the space vehicle; and
,remotely reconfiguring a field programmable gate array to perform a new signal processing task.
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9. A reconfigurable digital processing system for use in space to permit remote reconfiguration of a space vehicle-born processor, comprising:
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a field programmable gate array functioning as a signal processor for performing a signal processing task aboard said space vehicle;
a receiver on said space vehicle for reviewing uploaded commands for reconfiguring said field programmable gate array; and
,a field programmable gate array configuring unit coupled to said receiver for reconfiguring said field programmable gate array responsive to said uploaded commands, whereby a field programmable gate array aboard said space vehicle can be reconfigured from a remote location. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A reconfigurable digital processing system, comprising:
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a card having a number of field programmable gate arrays thereon;
a control unit for controlling the configuration of said field programmable gate arrays;
a configuration bus coupled between said control unit and said field programmable gate arrays;
a bus interface coupled to said field programmable gate arrays; and
,a shadow interconnect between said field programmable gate arrays for connecting said arrays together to perform parallel processing tasks. - View Dependent Claims (20)
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Specification