Random access imaging sensor

• US 20040155175A1
• Filed: 02/03/2004
• Published: 08/12/2004
• Est. Priority Date: 02/03/2003
• Status: Active Grant

• Current Assignee: Danbury Mission Technologies, LLC (AMERGINT Technologies, Inc.)
• Original Assignee: Goodrich Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: McNulty, Peter C.
• Granted Patent: US 7,223,954 B2
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: H04N 25/443 by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals

Abstract

A circuit includes a decoder for receiving an address within an address space of a processor and for accessing a pixel in an active pixel sensor array based on the address. The decoder maps the active pixel sensor array to the address space. The circuit can also provide sequencing of these addresses such that a group of pixels can be read out without additional addressing from a processor. There is also provided a method of processing pixel imperfections in real time. Pixel integration can be programmed on any single pixel or group of pixels in the array as well as windowed readout. A method of target discrimination is also disclosed.

Claims

1. A circuit comprising:

a decoder for receiving an address within an address space of a processor and for accessing a pixel in an active pixel sensor array based on said address,

wherein said decoder maps said active pixel sensor array to said address space.

2. The circuit of claim 1, wherein said decoder converts said address into a row signal and a column signal that designate a position of said pixel in said active pixel sensor array.

3. The circuit of claim 1, further comprising:

a module for receiving a start address and an end address that designates a portion of said active pixel sensor array,

wherein said module uses said start address and said end address to present a sequence of addresses that said decoder uses to sequentially access a plurality of pixels in said portion.

4. The circuit of claim 1, further comprising a module for correcting for a condition selected from the group consisting of:

an offset of said pixel, and a gain of said pixel.

5. The circuit of claim 1,

wherein said active pixel sensor array senses an image, and

wherein said circuit is employed for tracking a target in said image.

6. The circuit of claim 5, wherein said target is a star.

7. The circuit of claim 1,

wherein said pixel is one of a plurality of pixels in said active pixel sensor array, and

wherein said circuit provides a signal to simultaneously extract charges from said plurality of pixels.

8. The circuit of claim 7, wherein said plurality of pixels form a row of pixels in said active pixel sensor array.

9. The circuit of claim 7, wherein said charges are added together to yield a sum.

10. The circuit of claim 9, further comprising a module for comparing said sum to a threshold value to determine whether a target image is represented by said plurality of pixels.

11. An integrated circuit, comprising:

an active pixel sensor array, and

a decoder for receiving an address within an address space of a processor and for accessing a pixel of said active pixel sensor array based on said address,

wherein said decoder maps said active pixel sensor array to said address space.

12. The integrated circuit of claim 11, further comprising a converter for representing a charge read from said pixel as a digital value.

13. The integrated circuit of claim 11, wherein said active pixel sensor array is configured of complementary metal oxide semiconductor (CMOS) devices.

14. The integrated circuit of claim 11, wherein said decoder accesses said pixel by converting said address into a row signal and a column signal to designate a position of said pixel in said active pixel sensor array.

15. The integrated circuit of claim 11, further comprising a module for receiving a start address and an end address that designates a portion of said active pixel sensor array, wherein said module uses said start address and said end address to present a sequence of addresses to said decoder to access pixels in said portion.

16. The integrated circuit of claim 11, further comprising a module to correct for a condition selected from the group consisting of:

an offset of said pixel, and a gain of said pixel.

17. The integrated circuit of claim 11, further comprising an amplifier for amplifying a charge read from said pixel.

18. The integrated circuit of claim 11, wherein said pixel comprises an electron well and a gate to control integration time over said electron well.

19. The integrated circuit of claim 11, wherein said pixel comprises a photodiode to collect a charge.

20. The integrated circuit of claim 11, wherein said active pixel sensor array senses an image, and wherein said integrated circuit is employed for tracking a target in said image.

21. The integrated circuit of claim 20, wherein said target is a star.

22. An interface comprising a module that enables a processor to access a pixel circuit in an active pixel sensor array by direct memory access.

23. The interface of claim 22, wherein said module comprises a decoder for receiving an address from said processor and for converting said address into a row signal and a column signal that designate a position of said pixel circuit in said active pixel sensor array.

24. The interface of claim 22, further comprising a module for receiving a start address and an end address and for sequentially accessing a plurality of pixel circuits in a portion of said active pixel sensor array based on said start address and said end address.

25. The interface of claim 22, further comprising a module for correcting for a condition selected from the group consisting of:

an offset of said pixel circuit, and a gain of said pixel circuit.

26. The interface of claim 22,

wherein said active pixel sensor array senses an image, and

wherein said interface is employed for tracking a target in said image.

27. The interface of claim 26, wherein said target is a star.

28. The interface of claim 22,

wherein said pixel circuit is one of a plurality of pixel circuits in said active pixel sensor array, and

wherein said interface provides a signal to simultaneously extract charges from said plurality of pixel circuits.

29. The interface of claim 28, wherein said plurality of pixel circuits form a row of pixel circuits in said active pixel sensor array.

30. The interface of claim 28, wherein said charges are added together to yield a sum.

31. The interface of claim 30, further comprising a module for comparing said sum to a threshold value to determine whether a target image is represented by said plurality of pixel circuits.

32. A system comprising:

an active pixel sensor array;

a decoder for accessing a pixel of said active pixel sensor array based on an address;

a converter for representing a charge read from said pixel as a digital value; and

a microprocessor for providing said address and receiving said digital value,

wherein said address is within an address space of said microprocessor, and

wherein said decoder maps said active pixel sensor array to said address space.

33. The system of claim 32, wherein said active pixel sensor array is configured of complementary metal oxide semiconductor (CMOS) devices.

34. The system of claim 32, wherein said decoder accesses said pixel by converting said address into a row signal and a column signal to designate a position of said pixel in said active pixel sensor array.

35. The system of claim 32,

wherein said microprocessor provides a start address and an end address that designates a portion of said active pixel sensor array, and

wherein said system further comprises a module that uses said start address and said end address to present a sequence of addresses to said decoder to access pixels in said portion.

36. The system of claim 32, further comprising a module to correct for a condition selected from the group consisting of:

an offset of said pixel, and a gain of said pixel.

37. The system of claim 32, further comprising an amplifier for amplifying a charge read from said pixel.

38. The system of claim 32, wherein said active pixel sensor array senses an image, and said system is employed for tracking a target in said image.

39. The system of claim 38, wherein said target is a star.

40. The system of claim 32, wherein said pixel wherein said microprocessor controls an integration time for a window that includes said pixel.

41. The system of claim 32, wherein said microprocessor controls an integration time on a group of pixels of said active pixel sensor array.

42. The system of claim 32, wherein said microprocessor addresses a sub-frame of view region of said active pixel sensor array.

43. The system of claim 32, wherein said microprocessor manages a first sub-frame of said active pixel sensor array and a second sub-frame of said active pixel sensor array.

44. The system of claim 43, wherein said first sub-frame has a first integration time and said second sub-frame has a second integration time.

45. The system of claim 43, wherein said first and second sub-frame of view regions overlap one another.