Liquid crystal display unit

• US 20040156604A1
• Filed: 03/15/2004
• Published: 08/12/2004
• Est. Priority Date: 02/14/2002
• Status: Active Grant

• Current Assignee: Japan Display West Incorporated (Japan Display Incorporated)
• Original Assignee: Japan Display West Incorporated (Japan Display Incorporated)
• Inventors: Tanaka, Tsutomu, Yamaguchi, Hidemasa, Nakamura, Shinji, Ino, Masumitsu, Fukunaga, Yoko
• Granted Patent: US 8,629,958 B2
• Time in Patent Office: Days
• US Class Current: 385/114
• CPC Class Codes: G02F 1/133555 Transflectors
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes

Abstract

A liquid crystal display device capable of dealing with highly definition display and securing both of transmission type display luminance and reflection type display luminance, wherein the Cs on-gate structure is adopted, and a light reflectance is set to be in a range of 1% or more and 30% or less and a light transmittance is set to be in a range of 4% or more and 10% or less on the display panel formed by arranging in matrix a plurality of pixel regions 4 having a reflection region A for reflection type display by reflection of an ambient light and a transmission region B for transmission type display by transmission of light from a light source provided inside.

Claims

1. A liquid crystal display device comprising a display panel including a plurality of pixel regions arranged in matrix on a substrate, a plurality of transistors formed for each pixel region and arranged in matrix, a plurality of gate lines for connecting gate electrodes of the plurality of transistors, a plurality of data signal lines for connecting first electrodes of the plurality of transistors, a storage capacitor wherein one electrode is connected to a second electrode of said transistor, a storage capacitor line for connecting the other electrode of said storage capacitor, and a liquid crystal layer arranged between one electrode of said pixel region connected to the second electrode of said transistor and the other electrode opposing to the electrode, wherein:

said storage capacitor is connected to a gate line of the former stage and has the Cs-on-gate structure wherein a storage capacitor is superimposed on the gate line;

a reflection region and transmission region are arranged in parallel on each of said pixel regions; and

a reflectance of light on said display panel by said reflection region is 1% or more and 30% or less, and a transmittance of light on said display panel by said transmission region is 4% or more and 10% or less.

2. A liquid crystal display device as set forth in claim 1, wherein light amount of the display light is 20 cd/m² or more and 2000 cd/m² or less under a condition that irradiation of light of a light source is 500 cd/m² or more and 25000 cd/m² or less on said display panel.

3. A liquid crystal display device as set forth in claim 1, wherein light amount of the display light is 20 cd/m² or more and 1000 cd/m² or less under a condition that irradiation of a light of an ambient light is 2000 lx or more and 50000 lx or less on said display panel.

4. A liquid crystal display device as set forth in claim 1, wherein said transistor is a thin film transistor having a semiconductor layer of low temperature polycrystalline silicon.

5. A liquid crystal display device as set forth in claim 1, wherein said reflection region is formed by a metal film having a high reflectance.

6. A liquid crystal display device as set forth in claim 1, wherein an area of said transmission region is 40% or more of said entire pixel region and an area of said reflection region is 1% or more and 60% or less of said entire pixel region in said pixel region.

7. A liquid crystal display device as set forth in claim 1, wherein an aperture ratio of said transmission region is 40% or more and less than 100% of said entire pixel region in said pixel region

8. A liquid crystal display device as set forth in claim 1, wherein said reflection region is formed on a region immediately on a region of any one of interconnect region of said gate line, interconnect region of said data signal line, an interconnect region of said storage capacitor line, and a formation region of said transistor, or combination of some of them.

9. A liquid crystal display device as set forth in claim 1, wherein a polarity of a counter potential is inverted for every horizontal scanning period.

10. A liquid crystal display device as set forth in claim 1, comprising a selector switch for performing time-sharing driving on said signal lines.