Method of forming a low-K dual damascene interconnect structure
First Claim
1. A method of forming a low K interconnect structure, comprising:
- providing a film stack comprising a lower low K dielectric layer having a hardened top portion, an upper low K dielectric layer, an etch stop layer and a hard mask;
patterning the hard mask to define a trench;
depositing and patterning a photoresist layer that defines a via within the trench;
etching the via into the upper low K dielectric layer and the hardened top portion of the lower low K dielectric layer;
stripping the photoresist layer; and
etching a trench into the upper low K dielectric layer as defined by the hard mask while simultaneously etching a via into the lower low K dielectric layer using the hardened portion as a mask for the via.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
66 Citations
46 Claims
-
1. A method of forming a low K interconnect structure, comprising:
-
providing a film stack comprising a lower low K dielectric layer having a hardened top portion, an upper low K dielectric layer, an etch stop layer and a hard mask;
patterning the hard mask to define a trench;
depositing and patterning a photoresist layer that defines a via within the trench;
etching the via into the upper low K dielectric layer and the hardened top portion of the lower low K dielectric layer;
stripping the photoresist layer; and
etching a trench into the upper low K dielectric layer as defined by the hard mask while simultaneously etching a via into the lower low K dielectric layer using the hardened portion as a mask for the via. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method of etching a low K material comprising:
-
hardening a portion of a low K material;
patterning the hardened portion to form at least one opening to low K material that is unhardened; and
etching the unhardened low K material in the at least one openings. - View Dependent Claims (15, 16, 17)
-
-
18. In an etch chamber that is designed to etch dielectric materials, a method of etching metal and dielectric materials within said etch chamber comprising:
-
supplying a substrate comprising at least one layer of metal and at least one layer of dielectric material to the etch chamber;
applying a first etchant gas to the etch chamber to etch the at least one metal layer;
exhausting the first etchant gas from the etch chamber; and
applying a second etchant gas to the etch chamber to etch the at least one dielectric layer. - View Dependent Claims (19, 20, 21, 22)
-
-
23. A method of forming an interconnect structure comprising:
-
supplying a substrate comprising a layer of material having an opening formed therein;
depositing an antireflective coating layer in the opening and atop the layer until a top surface of the antireflective coating layer is substantially planar; and
depositing a mask atop the antireflective coating material. - View Dependent Claims (24, 25, 26)
-
-
27. A method of correcting a misalignment between a via and a trench comprising:
-
depositing a first mask layer atop a material layer;
patterning a trench pattern in the first mask layer;
depositing a second mask layer atop the patterned first mask layer;
patterning a via pattern in the second mask layer, where said via pattern is misaligned and partially overlaps the first mask layer;
etching a via corresponding to the via pattern that removes a portion of the first mask layer that is overlapped by the via pattern and removes a portion of the material layer that corresponds to the via pattern;
stripping the second mask layer; and
etching a trench into the material layer that corresponds with the trench pattern. - View Dependent Claims (28, 29, 30, 31)
-
-
32. A method of forming a low K interconnect structure, comprising:
-
providing a film stack comprising a lower low K dielectric, an upper low K dielectric layer, and a hard mask;
patterning the hard mask to define a trench;
depositing and patterning a photoresist layer that defines a via within the trench;
etching the via into the upper low K dielectric layer and a portion of the lower low K dielectric layer;
stripping the photoresist layer; and
etching a trench into the upper low K dielectric layer as defined by the hard mask while simultaneously etching a via into the lower low K dielectric layer. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
-
Specification