High density 3d rail stack arrays and method of making
First Claim
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1. A semiconductor device, comprising:
- (a) a first field effect transistor, comprising;
(i) a first rail comprising a first channel region, a first gate insulating layer, and a first gate electrode, (ii) a first source region, and (iii) a first drain region, (b) a second field effect transistor, comprising;
(j) a second rail comprising a second channel region, a second gate insulating layer, and a second gate electrode, (ii) a second source region, and (iii) a second drain region, wherein the first rail comprises the second source region or the second drain region.
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Abstract
A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
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Citations
72 Claims
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1. A semiconductor device, comprising:
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(a) a first field effect transistor, comprising;
(i) a first rail comprising a first channel region, a first gate insulating layer, and a first gate electrode, (ii) a first source region, and (iii) a first drain region, (b) a second field effect transistor, comprising;
(j) a second rail comprising a second channel region, a second gate insulating layer, and a second gate electrode, (ii) a second source region, and (iii) a second drain region, wherein the first rail comprises the second source region or the second drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A monolithic three dimensional array of field effect transistors, comprising:
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(a) a substrate;
(b) a plurality of first rails disposed at a first height relative to the substrate in a first direction, wherein each of the plurality of first rails comprises a first heavily doped semiconductor layer of a first conductivity type;
(c) a plurality of second rails disposed in contact with the first rails, at a second height different from the first height, and in a second direction different from the first direction, wherein each of the plurality of second rails comprises a second heavily doped semiconductor layer of the first conductivity type; and
(d) a plurality of third rails disposed in contact with the second rails, in the first direction at a third height relative to the substrate such that the second rails are located between the first and the third rails, wherein each of the plurality of third rails comprises a third heavily doped semiconductor layer of the first conductivity type;
wherein portions of the plurality of second rails comprise gate electrodes of a plurality of first field effect transistors and source or drain regions of a plurality of second field effect transistors. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A monolithic three dimensional array of field effect transistors, comprising:
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(a) a substrate;
(b) a plurality of first rails disposed at a first height relative to the substrate in a first direction, wherein each of the plurality of first rails comprises a first heavily doped semiconductor layer of a first conductivity type;
(c) a plurality of second rails disposed at a second height different from the first height, and in a second direction different from the first direction, wherein each of the plurality of second rails comprises;
a second lightly doped semiconductor channel layer of a second conductivity type located in contact with the first rails;
a second heavily doped semiconductor layer of the first conductivity type; and
a second gate insulating layer between and in contact with the second channel layer and the second heavily doped layer of the first conductivity type;
a second heavily doped semiconductor layer of the second conductivity type electrically connected to the second heavily doped semiconductor layer of the first conductivity type by a metal or a metal silicide layer;
(d) a plurality of third rails disposed in the first direction at a third height relative to the substrate, wherein each of the plurality of third rails comprises;
a third lightly doped semiconductor channel layer of the first conductivity type located in contact with the second heavily doped layer of the second conductivity type in the second rails;
a third heavily doped semiconductor layer of the second conductivity type;
a third heavily doped semiconductor layer of the first conductivity type electrically connected to the third heavily doped semiconductor layer of the first conductivity type by a metal or a metal silicide layer; and
a third gate insulating layer between and in contact with the channel layer and the third heavily doped layer of the second conductivity type. - View Dependent Claims (34, 35, 36, 37)
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38. A semiconductor device, comprising:
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a first field effect transistor of a first polarity; and
a second field effect transistor of a second polarity;
wherein a gate electrode of the first transistor is electrically connected to a source or drain of the second transistor without any lateral interconnects.
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39. A monolithic three dimensional memory array of field effect transistors, comprising:
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(a) a substrate;
(b) a plurality of first rails disposed at a first height relative to the substrate in a first direction, wherein each of the plurality of first rails comprises a first heavily doped semiconductor layer of a first conductivity type;
(c) a plurality of second rails disposed in contact with the first rails at a second height different from the first height, and in a second direction different from the first direction, wherein each of the plurality of second rails comprises;
a second heavily doped semiconductor layer of the first conductivity type;
a second lightly doped semiconductor channel layer of the second conductivity type; and
a second charge storage region located between the second heavily doped semiconductor layer and the second lightly doped semiconductor layer; and
(d) a plurality of third rails disposed in the first direction at a third height relative to the substrate such that the second rails are located between the first and the third rails, wherein each of the plurality of third rails comprises;
a third heavily doped semiconductor layer of the first conductivity type;
a third lightly doped semiconductor channel layer of the second conductivity type; and
a third charge storage region located between the third heavily doped semiconductor layer and the third lightly doped semiconductor layer;
wherein;
the second lightly doped semiconductor layers in the second rails contact the first heavily doped semiconductor layers in the first rails; and
the third lightly doped semiconductor layers in the third rails contact the second heavily doped semiconductor layers in the second rails. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. A method of making a monolithic three dimensional field effect transistor array, comprising:
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forming a plurality of first rails disposed at a first height relative to a substrate in a first direction, wherein each of the plurality of first rails comprises a first heavily doped semiconductor layer of a first conductivity type;
forming a first insulating isolation layer over the first plurality of rails;
patterning the first isolation layer to form a plurality of first openings exposing upper portions of adjacent first rails;
forming a second lightly doped semiconductor layer of a second conductivity type over the patterned isolation layer such that transistor channel portions in the second lightly doped layer of the second conductivity type contact the first heavily doped layer of the first conductivity type through the first openings;
forming a second gate insulating layer over the second lightly doped semiconductor layer of the second conductivity type;
forming a second heavily doped semiconductor layer of the first conductivity type over the second gate insulating layer; and
patterning the second heavily doped layer of the first conductivity type, the second gate insulating layer, and the second lightly doped layer of the second conductivity type to form a plurality of second rails extending in a second direction different from the first direction. - View Dependent Claims (51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
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62. A monolithic three-dimensional array of active devices comprising odd and even levels of field effect transistors, wherein:
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odd levels comprise transistors of a first polarity;
even levels comprise transistors of a second polarity;
each transistor comprises a gate electrode, source, and drain, wherein the gate electrodes, sources, and drains of the transistors of at least two levels comprise polysilicon;
current flows between the source and the drain in a first direction through transistors of the first polarity; and
current flows between the source and the drain in a second direction not parallel to the first direction through transistors of the second polarity. - View Dependent Claims (63, 64)
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65. A semiconductor device, comprising:
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a first transistor having a gate electrode, source, channel, and drain oriented in a first direction;
a second transistor having a gate electrode, source, channel, and drain oriented in a second direction different from said first direction; and
wherein the gate electrode of said first transistor and the source of said second transistor are disposed in a portion of a first rail. - View Dependent Claims (66, 67, 68)
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69. A semiconductor device comprising a first rail, said first rail comprising:
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a gate electrode of a first field effect transistor; and
a source or drain of a second field effect transistor;
wherein said first transistor and said second transistor are oriented in non-parallel directions. - View Dependent Claims (70, 71, 72)
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Specification