Method and apparatus for adjusting the performance of a synchronous memory system

• US 20040168036A1
• Filed: 03/10/2003
• Published: 08/26/2004
• Est. Priority Date: 10/10/1997
• Status: Active Grant

• Current Assignee: Bruno Werner Garlepp, Clemenz Portmann, Donald C. Stark, Ely K. Tsern, Kevin S. Donnelly, Pak Shing Chau, Paul G. Davis, Richard M. Barth, Stefanos Sidiropoulos
• Original Assignee: Bruno Werner Garlepp, Clemenz Portmann, Donald C. Stark, Ely K. Tsern, Kevin S. Donnelly, Pak Shing Chau, Paul G. Davis, Richard M. Barth, Stefanos Sidiropoulos
• Inventors: Barth, Richard M., Tsern, Ely K., Sidiropoulos, Stefanos, Stark, Donald C., Portmann, Clemenz, Davis, Paul G., Donnelly, Kevin S., Chau, Pak Shing, Garlepp, Bruno Werner
• Granted Patent: US 7,149,856 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.

Claims

1. A method for controlling performance of a memory system, the memory system including a master device and slave memory devices coupled to the master device via a memory channel, the method comprising the steps of:

sending an operating information from the master device via the memory channel to at the slave memory devices;

receiving the operating information and storing it in at least one of the slave memory devices; and

using the operating information to tune circuitry within the slave memory devices to improve the performance of the memory system.

2. A method for controlling performance of a memory system according to claim 1 wherein the operating information specifies frequency information.

3. A method for controlling performance of a memory system according to claim 2 wherein the frequency information is an operating clock frequency of the memory system.

4. A method for controlling performance of a memory system according to claim 2 wherein the frequency information is a frequency range from among a plurality of frequency ranges, the frequency range including an operating clock frequency of the memory system.

5. A method for controlling performance of a memory system according to claim 2 wherein the frequency information specifies a period of a cycle of an operating clock frequency.

6. A method for controlling performance of a memory system according to claim 1 wherein the operating information includes information specifying one or more of the following system parameters:

operating clock frequency, supply voltage, temperature, electrical length of the memory channel, or physical length of the memory channel.

7. A method for controlling performance of a memory system according to claim 6 wherein the master device includes a detector for determining one or more of the system parameters.

8. A method for controlling performance of a memory system according to claim 6 further comprising the step of:

the the slave memory devices determining information about one or more of the following local parameters, local to each slave memory device;

supply voltage, temperature, process conditions, or sheet resistance.

9. A method for controlling performance of a memory system according to claim 8 wherein the information about the local parameters is used along with the operating information from the master device to tune the circuitry within the slave memory devices.

10. A method for controlling performance of a memory system according to claim 1 wherein the memory system is a synchronous memory system.

11. A method for controlling performance of a memory system according to claim 10 wherein the circuitry within the slave memory devices are clock recovery and alignment circuits.

12. A method for controlling performance of a memory system according to claim 11 wherein the clock recovery and alignment circuits include at least one of the following circuits:

a delay-locked loop or a phase-locked loop.

13. A method for controlling performance of a memory system according to claim 12 wherein the step of tuning the performance of the memory system includes the step of adjusting the locking frequency range of the clock recovery and alignment circuits to include the operating clock frequency of the memory system.

14. A method for controlling performance of a memory system according to claim 10 wherein the channel includes high-speed lines and lower-speed sideband lines, and wherein the operating information is sent via the lower-speed sideband lines to tune the performance of signals on the high-speed lines.

15. A method for controlling performance of a memory system according to claim 14 wherein the step of tuning the performance of the memory system includes reducing a jitter of the signals on the high-speed lines.

16. A method for controlling performance of a memory system according to claim 10 wherein the channel includes high-speed lines and wherein the operating information is sent via the high-speed sideband lines to tune the performance of signals thereon.

17. A method for controlling performance of a memory system according to claim 16 wherein the step of tuning the performance of the memory system includes improving the timing margin of the signals on the high-speed lines.

18. A memory system comprising:

a master device;

a of slave memory device;

a memory channel coupling the master device to the slave memory device such that the slave memory device receives a system operating information from the master device via the memory channel;

the slave memory device including means for tuning circuitry within the slave memory device such that the performance of the memory system is improved.

19. The memory system of claim 18 wherein the operating information specifies an operating clock frequency of the memory system.

20. The memory system of claim 19 wherein the operating information specifies a frequency range from among a plurality of frequency ranges, the frequency range including the operating clock frequency of the memory system.

21. The memory system of claim 19 wherein the operating information specifies the period of the operating clock frequency.

22. The memory system of claim 18 wherein master device further comprises a detector for determining system parameters.

23. The memory system of claim 22, wherein the system parameters include:

operating clock frequency, supply voltage, temperature, electrical length of the memory channel, or physical length of the memory channel.

24. The memory system of claim 23 wherein the operating information includes one or more of said system parameters.

25. The memory system of claim 23 wherein the slave memory device includes a detector for determining local system parameters.

26. The memory system of claim 25, wherein said local system parameters include:

supply voltage, temperature, process conditions, or sheet resistance.

27. The memory system of claim 25 wherein the slave memory device further includes means for using the local parameters along with the operating information from the master device to tune the circuitry within the slave memory device.

28. The memory system of claim 18 wherein the memory system is a synchronous memory system.

29. The memory system of claim 28 wherein the circuitry within the slave memory device is a clock recovery and alignment circuit.

30. The memory system of claim 29 wherein the clock recovery and alignment circuit includes at least one of the following circuits:

a delay-locked loop or a phase-locked loop.

31. The memory system of claim 29 wherein the clock recovery and alignment circuit reduces a jitter of signals on the high-speed lines.

32. The memory system of claim 29 wherein clock recovery and alignment circuit improves a timing margin of signals on the high-speed lines.

33. The memory system of claim 18 wherein the memory channel includes high speed lines and lower speed sideband lines.

34. The memory system of claim 33, wherein the operating information is sent via the lower-speed sideband lines to tune the performance of signals on the high-speed lines.

35. The memory system of claim 33 wherein the operating information is sent via the high-speed lines to tune the performance of signals thereon.