Method and apparatus for controlling an external RF device with a dual processor system

• US 20040177188A1
• Filed: 01/07/2004
• Published: 09/09/2004
• Est. Priority Date: 01/08/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Seong-Ho
• Granted Patent: US 7,269,676 B2
• Time in Patent Office: Days
• US Class Current: 710/113
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A method and apparatus for controlling a device by a serial link from a dual processor system. The configuration of the circuit is simplified and efficiency is enhanced by using independent internal buses and serial link control hardware for each processor and by selecting the active control hardware through arbitration. An MCU and a DSP can operate asynchronously and use their respective internal bus at the same time.

Claims

1. An apparatus for outputting a serial link to control a device, comprising:

a first processor operatively connected to a first bus; and

a second processor operatively connected to a second bus;

a first control circuit for receiving and storing an address, a read/write strobe signal and data outputted from the first processor through the first bus, and outputting serial data derived from the data outputted from the first processor;

a second control circuit for receiving and storing an address, a read/write strobe signal and data outputted from the second processor through the second bus, and outputting serial data derived from the data outputted from the first processor;

an arbiter for receiving serial link request signal from each of the first and second control circuits, and for outputting at least one of a serial link grant signal and an MUX selection signal according to a predetermined priority; and

a multiplexer(MUX) for selectively outputting the selected serial data from either one of the first or second control circuits in response to the MUX selection signal from the arbiter.

2. The apparatus of claim 1, wherein the first control circuit comprises:

a first control register for receiving and storing the address, the read/write strobe signal and the data inputted from the first processor through the first bus, and for transmitting a serial link request signal to the arbiter;

a first shift register for receiving the data stored at the first control register and for converting the data into serial data, and for outputting the serial data in response to the serial link grant signal applied from the arbiter.

3. The apparatus of claim 2, wherein the second control circuit comprises:

a second control register for receiving and storing the address, the read/write strobe signal and the data inputted from the second processor through the second bus, and for transmitting the serial link request signal to the arbiter;

a second shift register for receiving the data stored at the second control register and for converting the data

into serial data, and outputting the serial in response to the serial link grant signal applied from the arbiter.

4. The apparatus of claim 3, wherein at least one of the first and second control circuits is implemented as a field programmable gate array (FPGA).

5. The apparatus of claim 3, wherein both of the first and second control circuits further outputs a serial clock signal of the same frequency for regulating the transmission of the serial data.

6. The apparatus of claim 5, wherein:

the first control circuit further comprises a first divider for dividing a first system clock signal provided from the first processor to generate and output the serial clock signal; and

the second control circuit comprises a second divider for dividing a second system clock signal provided from the second processor to generate and output the serial clock signal.

7. The apparatus of claim 6, wherein the first processor and the second processor operate mutually asynchronously from each other.

8. The apparatus of claim 3, wherein the operative frequency of the system clock of the first processor is not equal to the operative frequency of the system clock signal of the second processor.

9. The apparatus of claim 8, wherein frequency of a first system clock signal of the first processor is 39 MHz and the frequency of a second system clock signal of the second processor is 65 MHz.

10. The apparatus of claim 8 wherein the serial clock signal is equal to or less than 13 MHz.

11. The apparatus of claim 3 wherein the device is a radio frequency (RF) device.

12. The apparatus of claim 3 wherein the first processor is a microprocessor unit (MPU) and the second processor is a digital signal processor (DSP).

13. A method for controlling a device through a serial link with a dual processor system, said method comprising the steps of:

enabling a first processor operatively connected to a first control circuit through a first bus, and a second processor operatively connected to a second control circuit through a second bus, to independently access respective address, a read/write strobe signal and data through the first and second buses regardless of a serial link use grant;

transmitting a serial link request signal output from the first or second control circuit to an arbiter for selecting which of the first and second processors shall be the source of the data to be transmitted by a serial link to control the device; and

transmitting serial data, and a serial enable signal, and a serial clock signal, outputted from one of the first and second control circuits, to the device when a serial link grant signal is applied from the arbiter by a predetermined priority.

14. The method of claim 13 wherein the device is a radio frequency (RF) device.

15. The method of claim 13 wherein the first processor is an microprocessor unit (MPU) and the second processor is a digital signal processor (DSP).

16. The method of claim 13, wherein the first control circuit receives and stores an address, a read/write strobe signal and data inputted from the first processor through the first bus, and transmits the serial link request signal to the arbiter.

17. The method of claim 16, wherein the second control circuit receives and stores an address, a read/write strobe signal and data inputted from the second processor through the second bus, and transmits the serial link request signal to the arbiter.

18. The method of claim 17, wherein both of the first and second control circuits further output a serial clock signal of the same frequency for regulating the transmission of the serial data.

19. The method of claim 18, wherein:

the first processor and the second processor operate mutually asynchronously from each other;

or

the operative frequency of the system clock of the first processor is not equal to the operative frequency of the system clock signal of the second processor.