PRESERVING TEOS HARD MASK USING COR FOR RAISED SOURCE-DRAIN INCLUDING REMOVABLE/DISPOSABLE SPACER
First Claim
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1. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising the steps of:
- (a) providing a material stack atop a surface of a semiconductor substrate, said material stack comprising an oxide hard mask located atop a gate conductor, which is located atop a gate dielectric;
(b) patterning said oxide hard mask and said gate conductor of said material stack;
(c) forming a disposable spacer on at least each sidewall of said patterned gate conductor;
(d) removing portions of said gate dielectric not protected by said disposable spacers and said patterned gate conductor to expose portions of said semiconductor substrate, wherein said removing comprises a chemical oxide removal step;
(e) forming raised source/drain regions in exposed portions of said semiconductor substrate; and
(f) removing said disposable spacers to expose portions of said semiconductor substrate abutting the patterned gate conductor.
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Abstract
The present invention provides a method for preserving an oxide hard mask for the purpose of avoiding growth of epi Si on the gate stack during raised source/drain formation. The oxide hard mask is preserved in the present invention by utilizing a method which includes a chemical oxide removal processing step instead of an aqueous HF etchant.
28 Citations
24 Claims
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1. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising the steps of:
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(a) providing a material stack atop a surface of a semiconductor substrate, said material stack comprising an oxide hard mask located atop a gate conductor, which is located atop a gate dielectric;
(b) patterning said oxide hard mask and said gate conductor of said material stack;
(c) forming a disposable spacer on at least each sidewall of said patterned gate conductor;
(d) removing portions of said gate dielectric not protected by said disposable spacers and said patterned gate conductor to expose portions of said semiconductor substrate, wherein said removing comprises a chemical oxide removal step;
(e) forming raised source/drain regions in exposed portions of said semiconductor substrate; and
(f) removing said disposable spacers to expose portions of said semiconductor substrate abutting the patterned gate conductor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising the steps of:
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(a) providing a material stack atop a surface of a semiconductor substrate, said material stack comprising an oxide hard mask located atop a gate conductor, which is located atop a gate dielectric;
(b) patterning said oxide hard mask and said gate conductor of said material stack;
(c) performing a post etch cleaning step utilizing a first chemical oxide removal (COR) step;
(d) forming a disposable spacer on at least each sidewall of said patterned gate conductor;
(e) removing portions of said gate dielectric not protected by said disposable spacers and said patterned gate conductor to expose portions of said semiconductor substrate, wherein said removing comprises a second COR step;
(f) forming raised source/drain regions in exposed portions of said semiconductor substrate; and
(g) removing said disposable spacers to expose portions of said semiconductor substrate abutting the patterned gate conductor. - View Dependent Claims (21, 22, 23, 24)
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Specification