Signal processing circuit, image sensor IC, and signal processing method
First Claim
1. A signal processing circuit, comprising:
- a sample/hold circuit for sampling an input signal separately inputted for a time interval of the first half and for a time interval of the second half for the time interval of the first half and for holding the inputted signal for the time interval of the second half;
a subtracter for taking a difference between the sampled and held signal and the inputted signal; and
a voltage clamp circuit for receiving as its input a signal from the subtracter, wherein the voltage clamp circuit carries out clamping for a part of or all of the time interval of the first half.
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Accused Products
Abstract
To provide an image sensor IC which is small in fixed pattern noise. The present invention includes: a sample/hold circuit for separately receiving as its input an optical signal obtained due to storage of electric charges generated due to light incident upon a photoelectric conversion unit, and a signal becoming a reference for the photoelectric conversion unit for a time interval of the first half and for a time interval of the second half to sample these signals for the time interval of the first half and to hold these signals for the time interval of the second half; a subtracter for taking a difference between the sampled and held signal and the inputted signal; and a circuit for clamping a signal from the subtracter for the time interval of the first half.
22 Citations
20 Claims
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1. A signal processing circuit, comprising:
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a sample/hold circuit for sampling an input signal separately inputted for a time interval of the first half and for a time interval of the second half for the time interval of the first half and for holding the inputted signal for the time interval of the second half;
a subtracter for taking a difference between the sampled and held signal and the inputted signal; and
a voltage clamp circuit for receiving as its input a signal from the subtracter, wherein the voltage clamp circuit carries out clamping for a part of or all of the time interval of the first half. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An image sensor, comprising:
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read means for reading out an optical signal and a reference signal to a common signal line, wherein the optical signal is obtained due to storage of electric charges generated due to light incident upon photoelectric converter and the reference signal is becoming a reference for the photoelectric converter;
a sample/hold circuit for receiving as its input a signal from the common signal line; and
a subtracter for taking and amplifying a difference between the sampled and held signal and the inputted signal.
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9. An image sensor, comprising:
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a first hold circuit for holding an optical signal obtained due to storage of electric charges generated due to light incident upon photoelectric converter;
a second hold circuit for holding a reference signal becoming a reference for the photoelectric converter;
read means for reading out the optical signal and the reference signal which are held in order to a common signal line;
a sample/hold circuit for receiving as its input a signal from the common signal line; and
a subtracter for taking and amplifying a difference between the sampled and held signal and the inputted signal.
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10. An image sensor IC, comprising:
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a photoelectric converter;
a signal processing circuit for receiving as its input a signal of the photoelectric converter;
a signal output terminal connected to an output terminal of the signal processing circuit;
a reference voltage terminal connected to a terminal at which a reference voltage for the signal processing circuit appears;
a reference voltage circuit; and
a resistor provided between the reference voltage circuit and the reference voltage terminal, the signal processing circuit comprising;
a sample/hold circuit for separately receiving as its input an optical signal and a reference signal for a time interval of the first half and for a time interval of the second half to sample the inputted signal for the time interval of the first half and to hold the sampled signal for the time interval of the second half, wherein the optical signal is obtained due to storage of electric charges generated due to light incident upon a photoelectric conversion area of photoelectric converter and the reference signal is becoming a reference for the photoelectric converter;
a subtracter for taking a difference between the sampled and held signal and the inputted signal; and
a voltage clamp circuit for clamping a signal from the subtracter for the time interval of the first half, wherein one of a reference voltage for the voltage clamp circuit and a reference voltage for the subtracter is supplied through the reference voltage terminal. - View Dependent Claims (11, 12)
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13. An image sensor IC, comprising:
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a plurality of photoelectric converter; and
a plurality of reset switches connected to the plurality of photoelectric converter for initializing the plurality of photoelectric converter, respectively, wherein the plurality of reset switches are electrically connected to a reference voltage terminal. - View Dependent Claims (14, 15, 16, 18)
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17. An image sensor IC, comprising:
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a plurality of photoelectric converter;
a plurality of reset switches connected to the plurality of photoelectric converter for initializing the plurality of photoelectric converter, respectively;
a first hold circuit for holding an optical signal obtained due to storage of electric charges generated due to light incident upon the photoelectric converter;
a second hold circuit for holding a reference signal becoming a reference for the photoelectric converter; and
read means for reading out the optical signal and the reference signal which are held in order to a common signal line, wherein the plurality of reset switches are electrically connected to a reference voltage terminal.
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19. A signal processing method for use in a signal processing circuit comprising at least:
- a sample/hold circuit for receiving its input an input signal having a time interval of the first half and a time interval of the second half;
a subtracter for receiving as its input a signal from the sample/hold circuit and the input signal; and
a voltage clamp circuit for receiving as its input a signal from the subtracter and a reference voltage, wherein;
the sample/hold circuit, for the time interval of the first half of the input signal, holds the input signal and outputs the held input signal to the subtracter;
the subtracter, for the time interval of the second half of the input signal, outputs a difference signal exhibiting a difference between a signal from the sample/hold circuit and the input signal to the clamp circuit; and
the voltage clamp circuit, for the time interval of the first half, clamps an output signal of the voltage clamp circuit to the reference voltage, and for the time interval of the second half, superimposes the difference signal on the reference voltage. - View Dependent Claims (20)
- a sample/hold circuit for receiving its input an input signal having a time interval of the first half and a time interval of the second half;
Specification