Low complexity channel decoders

• US 20040199856A1
• Filed: 04/21/2004
• Published: 10/07/2004
• Est. Priority Date: 06/12/2001
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Intel Corporation
• Inventors: Yellin, Daniel, Rainish, Doron
• Granted Patent: US 7,240,274 B2
• Time in Patent Office: Days
• US Class Current: 714/776
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/299 Turbo codes with short blocks
• CPC Class Codes: H03M 13/3905 Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing
• CPC Class Codes: H03M 13/6505 Memory efficient implementations
• CPC Class Codes: H03M 13/6577 Representation or format of variables, register sizes or word-lengths and quantization
• CPC Class Codes: H03M 13/6588 Compression or short representation of variables

Abstract

A packet of encoded data is received and decoded using a look-up table that stores information approximating output of an algorithmic decoding process.

Claims

1-22. -22. (Cancelled)

23. A method comprising:

receiving a packet of encoded symbols;

jointly quantizing multiple symbols;

decoding the jointly quantized symbols to obtain a result; and

decompressing the result into individual decoded symbols.

24. The method of claim 23 including decoding the jointly quantized symbols using a look-up table that approximates output of an algorithmic decoding process.

25. The method of claim 23 including decoding the jointly quantized symbols using a look-up table that approximates output a soft-input soft-output algorithmic decoding process, a soft-input hard-output algorithmic decoding process, a hard-input soft-output algorithmic decoding process, or a hard-input hard-output algorithmic decoding process.

26. An article comprising a computer-readable medium that stores computer executable instruction for causing a computer system, in response to receiving a packet of encoded symbols, to:

jointly quantize multiple ones of the symbols;

decode the jointly quantized symbols to obtain a result; and

decompress the result into individual decoded symbols.

27. The article of claim 26 including instructions for causing the computer system to decode the jointly quantized symbols using a look-up table that approximates output of an algorithmic decoding process.

28. The article of claim 26 including instructions for causing the computer system to decode the jointly quantized symbols using a look-up table that approximates output of a soft-input soft-output algorithmic decoding process, a soft-input hard-output algorithmic decoding process, a hard-input soft-output algorithmic decoding process, or a hard-input hard-output algorithmic decoding process.

29. An apparatus comprising:

a memory storing a look-up table that approximates output of an algorithmic decoding process; and

a processor configured to;

jointly quantize symbols received in a packet of encoded symbols;

decode the jointly quantized symbols to obtain a result; and

decompress the result into individual decoded symbols.

30. The apparatus of claim 29 wherein the look-up table stores information that approximates output of a soft-input soft-output algorithmic decoding process

31. The apparatus of claim 29 wherein the look-up table stores information that approximates output of a soft-input hard-output algorithmic decoding process.

32. The apparatus of claim 29 wherein the look-up table stores information that approximates output of a hard-input soft-output algorithmic decoding process.

33. The apparatus of claim 29 wherein the look-up table stores information that approximates output of a hard-input hard-output algorithmic decoding process.