Adaptive receivers for bit rate agile (BRA) and modulation demodulation (modem) format selectable (MFS) signals

• US 20040208243A1
• Filed: 04/23/2004
• Published: 10/21/2004
• Est. Priority Date: 08/10/1998
• Status: Active Grant

• Current Assignee: Kamilo Feher
• Original Assignee: Kamilo Feher
• Inventors: Feher, Kamilo
• Granted Patent: US 7,376,180 B2
• Time in Patent Office: Days
• US Class Current: 375/232
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates
• CPC Class Codes: H04B 7/0871 using different reception schemes, at least one of them being a diversity reception scheme
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 27/00 Modulated-carrier systems
• CPC Class Codes: H04L 27/0004 using wavelets
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/2637 with direct modulation of individual subcarriers
• CPC Class Codes: H04L 27/34 Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

Systems, apparatus, and methods for new generations of wireless systems, including multiple standard, interoperable Third-Generation (3G) and Second-Generation (2G), Spread Spectrum CDMA, WCDMA, GSM, Enhanced GSM systems and CSMA, TDMA and OFDM. Bit Rate Agile (BRA), Modulation and Code Selectable processing techniques of Gaussian Minimum Shift Keying (GMSK), Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (QAM), and of Mis-Matched demodulator filters in which the demodulator filter set is mismatched to the filter set of the signal modulator.

Claims

1. An adaptive equalizer structure comprising:

an interface receiver port to provide connection of received Bit Rate Agile (BRA) and Modulation Demodulation (Modem) Format Selectable (MFS) modulated signal to the pre-demodulation adaptive equalizer;

a pre-demodulation adaptive equalizer structure comprising BRA and MFS splitter, multiplier circuit and delay structure for delaying the modulated signal in one branch of the splitter and coupling the time delayed signal in one branch of the splitter and the said received modulated signal in the other branch of the splitter to a signal combiner;

a BRA and MFS signal combiner structure for combining the said delayed modulated signal and received modulated signal product;

a BRA and MFS demodulator structure for demodulating the combined delayed signal and received modulated signal; and

a BRA and MFS control signal processor for generation of and connection of said control signal to the said product multiplier circuit.

2. An adaptive equalizer and switchable delay structure comprising:

an interface receiver port to provide connection of received modulated Bit Rate Agile (BRA) and Modulation Demodulation (Modem) Format Selectable (MFS) modulated signal to a plurality of splitters, amplifiers, delay elements, signal combiners and signal switches for signal selection of said received modulated signal;

a demodulator structure for demodulating the selected received BRA and MFS modulated signal; and

a control signal processor for generation of said control signal to control the BRA and MFS signal selection.

3. A receiver structure for reception, demodulation, adaptive equalization and signal processing of Bit Rate Agile (BRA), Modulation Demodulation (Modem) Format Selectable (S) and Code Selectable (CS) modulated received signals comprising:

(a) means for input port for receiving input signal;

(b) means for a receiver interface unit for connection of the received signal to the BRA, MFS demodulator;

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) means for BRA, MFS and CS demodulation and signal processing;

(d) means for adaptive equalization selection and switched selection of the BRA, MFS and CS demodulated signal

4. A Bit Rate Agile (BRA), Modulation Demodulation (Modem) Format Selectable (MFS) and Code Selectable (CS) signal receiver, demodulator and adaptive equalizer structure comprising:

(a) an interface receiver port to provide connection of received BRA, MFS and CS filtered quadrature modulated signal to the demodulator;

(b) a demodulator structure to serve for signal demodulation of the signal; and

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) an adaptive equalizer structure for equalization and selection of the demodulated signal

5. An adaptive equalizer structure comprising:

(a) an interface receiver port to provide connection of received Bit Rate Agile (BRA), Modulation Demodulation (Modem) Format Selectable (MFS) and Code Selectable (CS) modulated signal to the pre-demodulation adaptive equalizer;

(b) a pre-demodulation BRA, MFS and CS adaptive equalizer structure comprising splitter, signal multiplier circuit and delay structure for generating a delayed signal and received modulated signal in the at least two splitter branches and coupling the signal time delayed product in one branch of the splitter and the received modulating signal in the other branch of the splitter to a signal combiner;

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) a signal combiner structure for combining the delayed control signal and received modulated signal product;

(d) a demodulator structure for demodulating the combined delayed control signal and received modulated signal product; and

(e) a control signal processor for generation of and connection of the BRA, MFS and CS control signal to the signal multiplier circuit.

6. An adaptive equalizer and switchable signal selection structure comprising:

(a) an interface receiver port to provide connection of received modulated Bit Rate Agile (BRA), Modulation Demodulation (Modem) Format Selectable (MFS) and Code Selectable (CS) signal to a splitter, for signal selection of one or more of the received Quadrature Phase Shift Keying (QPSK), Offset Quadrature Phase Shift Keying (OQPSK) or Gaussian Minimum Shift Keying (GMSK) modulated signals; and

(b) a demodulator structure for demodulating one or more than one of the selected received QPSK or OQPSK or GMSK signals.