WIRELESS COMMUNICATION SYSTEM WITHIN A SYSTEM ON A CHIP

• US 20040209575A1
• Filed: 04/19/2003
• Published: 10/21/2004
• Est. Priority Date: 04/19/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ventrone, Sebastian T., Norman, Jason M., Goodnow, Kenneth J., Masenas, Charles J., Harding, Riyon W.
• Granted Patent: US 7,103,320 B2
• Time in Patent Office: Days
• US Class Current: 455/90.3
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving

Abstract

A communication system (8) for transmitting data between cores (10) embedded in an integrated circuit on a silicon chip (12). Communication system (8) includes transmitter circuitry (24) for wirelessly transmitting data between cores (10) and receiver circuitry (26) for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry (24) and receiver circuitry (26) may include of a phase-locked loop circuit (28, 30) having a voltage-controlled oscillator (36). Each core (10) may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip (12) or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip (12). Groups of cores (17) may share transmitter and receiver circuitry (24 and 26).

Claims

1. A communication system for transmitting data between cores in an integrated circuit, the communication system comprising:

an integrated circuit containing a plurality of cores;

transmitter circuitry in said integrated circuit for wirelessly transmitting data between said cores; and

receiver circuitry in said integrated circuit for wirelessly receiving the transmission of data.

2. A system according to claim 1, wherein each of said transmitter circuitry and receiver circuitry transmits and receives data, respectively, on a frequency that is unique with respect to each of said plurality of cores.

3. A system according to claim 1, wherein each of said transmitter circuitry and receiver circuitry transmits and receives data, respectively, on the same frequency.

4. A system according to claim 1, wherein said transmitter and receiver circuitry are shared by groups of cores.

5. A system according to claim 1, wherein at least one of said transmitter circuitry and said receiver circuitry further comprises a phase-locked loop circuit having a voltage-controlled oscillator.

6. A system according to claim 1, further comprising a reference clock, wherein said transmitter circuitry and said receiver circuitry are in communication with said reference clock.

7. A system according to claim 1, wherein said receiver circuitry provides acknowledgement signals to said transmitter circuitry upon successful receipt of a transmission and retry signals to said transmitter circuitry upon unsuccessful receipt of a transmission.

8. A system according to claim 1, wherein said receiver circuitry is able to transmit busy signals to said transmitter circuitry when said receiver circuitry is busy receiving another transmission at the time said transmitter circuitry transmits data.

9. A system according to claim 1, wherein said transmitter circuitry is able to transmit data at the same time said receiver circuitry receives data.

10. A system according to claim 1, wherein transmitter circuitry in a single core from said plurality of cores transmits to receiver circuitry in at least two other cores from said plurality of cores.

11. A system according to claim 1, wherein each of said plurality of cores has an identification.

12. A system according to claim 11, wherein said identification may be dynamically re-configurable.

13. A system according to claim 11, wherein an identification tag including said identification may be included in the data.

17. A system according to claim 10, wherein said receiver circuitry includes a means to transmit at least one of acknowledgement signals to a transmitter circuitry upon successful receipt of a transmission, retry signals to a transmitter circuitry upon unsuccessful receipt of a transmission, and busy signals to a transmitter circuitry when said receiver are busy receiving another transmission at the time the transmitter circuitry transmits their data.

18. A system according to claim 10, wherein said transmitter circuitry is able to transmit data at the same time said receiver circuitry receives data.

14. A system on a chip comprising:

an integrated circuit containing a package of integrated components defining a system on a chip,

a plurality of cores defining a plurality of integrated subsystems within said system on a chip, said plurality of cores included in said package of integrated components; and

communication means for wirelessly exchanging data between said plurality of integrated subsystems, said communication means included in said package of integrated components.

15. A system according to claim 14, wherein said communication means includes transmitter and receiver circuitry and each of said transmitter circuitry and receiver circuitry transmits and receives data, respectively, on a frequency that is unique with respect to each of said plurality of subsystems.

16. A system according to claim 14, wherein at least one of said transmitter circuitry and said receiver circuitry further comprises a phase-locked loop circuit having a voltage-controlled oscillator.

19. A method of wirelessly transmitting data between cores in an integrated circuit, the method comprising the steps of:

providing an integrated circuit containing a plurality of cores;

wirelessly transmitting data between said plurality of cores; and

wirelessly receiving said data.

20. A method according to claim 19, further comprising the step of:

transmitting and receiving data on the same frequency for each of said plurality of cores.