Software management systems and methods for automotive computing devices

• US 20040221094A1
• Filed: 05/27/2004
• Published: 11/04/2004
• Est. Priority Date: 12/20/2000
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Drasnin, Sharon, Radko, Ronald Otto, Beckert, Richard Dennis
• Granted Patent: US 7,043,613 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

Methods and systems for operating automotive computing devices are described. In one embodiment, a small amount of static RAM (SRAM) is incorporated into an automotive computing device. The SRAM is battery-backed to provide a non-volatile memory space in which critical data, e.g. the object store, can be maintained in the event of a power loss. Circuitry is provided to ensure that the SRAM receives back up power from the battery at appropriate times. Software manages the SRAM and the other storage assembly components and makes use of virtual paging or virtual addressing techniques to keep track of where various pages, including object store pages, are stored in the system. The software knows where all of the object store pages are located so that in the event of a power loss, the page locations are known and hence the pages can be used when power is restored. The SRAM is advantageously used to maintain so-called “dirty pages” or pages that have been written to so that these pages are not lost in the event of a power interruption. Additionally, the software can also provide an orderly means by which pages in the SRAM can be written out to flash memory thereby avoiding unnecessary flash write operations which, in turn, increases the lifetime of the flash memory.

Claims

1. A method for facilitating fast start-up/shut-down of a computing device having a processor, volatile memory, non-volatile memory, and SRAM, the method comprising;

providing an object store for the computing device in the non-volatile memory;

wherein a fast lossless shut-down of the computing device may be accomplished by periodically writing data from the object store to a non-volatile medium during operation of the computing device.

2. The method of claim 1, wherein a fast start-up of the computing device may be accomplished by writing predetermined data from the object store to volatile memory prior to starting up the computing device.

3. The method of claim 1, wherein said periodically writing is accomplished by periodically writing object store pages to the non-volatile medium before the object store pages are dirtied.

4. The method of claim 1, wherein said periodically writing is accomplished by periodically writing object store pages to battery-backed SRAM before the object store pages are dirtied.

5. The method of claim 1, wherein said periodically writing is accomplished by periodically writing object store pages to flash memory.

6. The method of claim 1, wherein said periodically writing is accomplished by periodically writing object store pages to battery-backed SRAM before the object store pages are dirtied, and maintaining object store page location information in the battery-backed SRAM.

7. The method of claim 1, wherein said periodically writing comprises:

periodically writing object store pages to battery-backed SRAM before the object store pages are dirtied;

maintaining object store page location information in the battery-backed SRAM;

periodically flushing at least portions of the battery-backed SRAM to a flash memory to make room in the battery-backed SRAM for additional object store pages; and

responsive to said flusing, updating the object store page location information in the battery-backed SRAM.