Method for packaging circuits and packaged circuits

• US 20040221451A1
• Filed: 12/23/2003
• Published: 11/11/2004
• Est. Priority Date: 05/06/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Waf, Low Siu, Boon, Suan Jeung, Chua, Swee Kwang, Chia, Yong Poo, Koon, Eng Meow
• Granted Patent: US 7,712,211 B2
• Time in Patent Office: Days
• US Class Current: 29/854
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49167 : with deforming of conductive path
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49794 : Dividing on common outline

Abstract

A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Claims

1. A method, comprising:

providing a die;

providing a substrate having electrical signal terminals thereon;

fixing the die on the substrate;

forming electrical connections from die to the terminals; and

removing a backside of substrate to expose the terminals.

2. The method of claim 1, wherein providing a die includes providing a die including an integrated circuit memory device.

3. The method of claim 1, wherein fixing the die on the substrate includes applying adhesive to a top surface of the substrate, placing the die on the adhesive, and curing the adhesive to fix the die on the substrate top surface.

4. The method of claim 1, wherein providing the die includes providing a die having I/O pads on a top surface of the die.

5. A method, comprising:

forming active devices on a first substrate;

singulating the active devices;

forming electrical terminals on a second substrate;

coating the second substrate with an adhesive;

placing a plurality of active devices on the adhesive;

curing the adhesive;

electrically connecting the active devices to respective electrical terminals;

removing a backside of the second substrate to expose a backside of the electrical terminals; and

singulating the second substrate to form individual chip scale packages that include at least one active device and a portion of the second substrate.

6. The method of claim 5, wherein forming electrical terminals includes patterning a conductive layer on a top surface of the second substrate.

7. The method of claim 6, wherein patterning the conductive layer includes patterning a metal layer.

8. The method of claim 6, wherein forming electrical terminals includes planarizing the top surface of the second substrate.

9. The method of claim 6, wherein removing a backside of the second substrate includes backgrinding the second substrate.

10. The method of claim 9, wherein electrically connecting the active devices to respective electrical terminals includes routing a metal trace from a bond pad on top of the active device to the electrical terminal below the active device.

11. The method of claim 10, wherein routing the metal trace includes routing the metal trace to an electrical terminal at least partially beneath the active device.

12. The method of claim 5, wherein electrically connecting the active devices to respective electrical terminals includes filling gaps between the active devices with a non-conductive material.

13. The method of claim 12, wherein singulating the second substrate includes cutting through non-conductive material in the gaps between the active devices.

14. A method, comprising:

providing a substrate having electrical signal terminals thereon;

placing adhesive on a top surface of the substrate;

placing a die having top surface bond pads on adhesive to fix the die to the substrate;

forming castellation electrical connections from top surface bond pads to the substrate terminals; and

removing a backside of substrate to expose terminals.

15. The method of claim 14, wherein removing the backside of the substrate includes backgrinding the substrate.

16. The method of claim 14, wherein removing the backside of the substrate includes etching the back surface of the substrate.

17. The method of claim 14, wherein forming castellation electrical connections includes removing adhesive uncovered by a die from the top surface of the substrate and forming a trace from the top surface bond pads along the sides of the die to contact the substrate electrical signal terminal.

18. The method of claim 17, wherein forming the trace includes using metal redistribution to join the top surface bond pad and the substrate electrical signal terminal.

19. A method, comprising:

fixing a plurality of dice on a substrate over a plurality of package I/O terminals;

forming electrical connections from die bond pads to the package I/O terminals; and

removing a backside of the substrate to expose the package I/O terminals.

20. The method of claim 19, wherein forming electrical connections includes forming electrical connections between some of the package I/O terminals.

21. The method of claim 20, wherein forming electrical connections between some of the package I/O terminals includes interconnecting at least a first of the plurality of dice to at least a second of the plurality of dice.

22. The method of claim 21, wherein interconnecting includes interconnecting the first die that has a processor to the second die that has a memory.

23. The method of claim 22, wherein removing the backside includes singulating the first and second die from a remainder of the substrate to form a multi-chip module.

24. A method, comprising:

fixing a plurality of dice on a substrate over a plurality of package terminals such that adjacent die overlie common package terminals;

electrically connecting I/O pads of the dice to the plurality of package terminals;

removing a backside of the substrate to expose the plurality of package terminals; and

singulating the plurality of dice with a portion of the substrate directly beneath each die to form a chip scale package.

25. The method of claim 24, wherein singulating includes cutting through the common package terminals such that a first portion remains with a first of the plurality of dice and a second portion remains with a second of the plurality of die.

26. A method, comprising:

providing a sensor die having a sensing device and an I/O pad at a top surface;

providing a substrate having electrical signal terminals thereon;

fixing the die on the substrate;

forming electrical connections from the I/O pad of the die to the substrate terminals; and

removing a backside of substrate to expose the terminals.

27. The method of claim 26, wherein providing the sensor die includes providing a sensor die with an optical sensor in electrical communication with the I/O pad.

28. The method of claim 26, wherein fixing the die includes applying adhesive over the substrate, and curing the adhesive.

29. The method of claim 26, wherein forming electrical connections includes forming an aperture through the adhesive to the electrical signal terminals, and forming a conductive trace from the I/O pad down the side of the die to the electrical signal terminal of the substrate.

30. The method of claim 29, wherein removing the backside of the substrate includes singulating the die from the remainder of the substrate.

31. A method, comprising:

providing a die;

providing a substrate having electrical signal terminals thereon;

applying adhesive to a top surface of the substrate;

positioning the die on the adhesive at least partially over a first group of the electrical signal terminals;

curing the adhesive to fix the die to the substrate;

forming a via through the adhesive to the first group of electrical signal terminals;

forming electrical connections from die through the via to substrate terminals; and

removing a backside of substrate to expose a backside of the terminals.

32. The method of claim 31, wherein applying adhesive includes applying a polymide material on the top surface of the substrate.

33. The method of claim 31, wherein forming electrical connections includes forming a metal trace from I/O pads on a top surface of the die down the side of the die to the substrate terminals.

34. The method of claim 33, wherein forming the metal trace includes forming a metal trace from one of a group including copper and aluminum.

35. A chip-scale-packaging method, comprising:

singulating dice from a first wafer;

testing the singulated dice;

forming final I/O locations on a second wafer;

applying adhesive to a top surface of the second wafer;

placing a singulated die on the adhesive over the final I/O locations;

removing a back surface of the second wafer to expose the final I/O locations; and

connecting the singulated die to an electric circuit through the final I/O location.

36. The chip-scale-packaging method of claim 35, wherein removing the backside of the second wafer includes backgrinding the second wafer.

37. The chip-scale-packaging method of claim 35, wherein removing the backside of the second wafer includes etching the back surface of the second wafer.

38. The chip-scale-packaging method of claim 35, wherein removing the back surface of the second wafer includes separating the singulated die and a portion of the second wafer from a remainder of the second wafer.

39. A method, comprising:

providing a plurality of integrated circuit dice;

providing a substrate having electrical signal terminals thereon with at least two of the electrical signal terminals being interconnected;

fixing a first die on the substrate over a first group of the electrical signal terminals;

fixing a second die on the substrate over a second group of the electrical signal terminals;

forming electrical connections from first die to first group of electrical signal terminals;

forming electrical connections from second die to second group of electrical signal terminals;

removing a backside of substrate to expose the terminals; and

separating the first and second die from a remainder of the substrate with the first and second die being adapted to electrically communicate through at least the interconnected electrical signal terminals.

40. The method of claim 39, wherein separating the first and second die includes filling the gap between the first die and the second die with an insulative material.

41. The method of claim 40, wherein filling the gap includes filling the gap with an encapsulant.

42. The method of claim 40, wherein filling the gap includes filling the gap with a benzocyclobutene material.

43. The method of claim 40, wherein separating the first and second die includes forming a memory module.

44. A chip-scale-packaging method, comprising:

providing a first substrate having a plurality of dice;

providing a second substrate having a plurality of package level terminals on a top surface;

coating the top surface of the second substrate with an adhesive;

curing the adhesive to fix the second substrate on the first substrate;

forming electrical connections from dice on the first substrate to the package level terminals; and

removing a backside of second substrate to expose the backside of the package level terminals.

45. The method of claim 44, wherein removing the backside of the second substrate includes singulating the plurality of dice into chip-level-packages.

46. The method of claim 45, wherein singulating includes lazing the second substrate intermediate adjacent dice.

47. The method of claim 46, wherein lazing includes water jetting the second substrate.

48. The method of claim 45, wherein forming electrical connections includes forming a conductive trace from a top bond pad of a die along the side of the die to contact a package level terminal.

49. The method of claim 48, wherein forming the conductive trace includes forming a redistribution layer on the plurality of dice.

50. The method of claim 48, wherein forming the conductive trace includes forming a copper conductor from the top bond pad to the package level terminal.

51. The method of claim 48, wherein forming electrical connections includes removing the adhesive from in between adjacent dice to partially expose the package level terminals and thereafter forming the conductive trace.

52. A method, comprising:

providing a first substrate with a plurality of first dice separated by first saw streets;

providing a second substrate with a plurality of second dice separated by second saw streets;

applying an adhesive to a backside of the second substrate;

placing the first substrate on the adhesive such that the first saw streets align with the second saw streets;

curing the adhesive to fix the first substrate to the second substrate;

forming a plurality of through apertures in the aligned first and second saw streets;

forming electrical connections from the first dice on the first substrate to the second dice on the second substrate; and

singulating aligned first and second dice from a remainder of the fixed first and second substrates.

53. The method of claim 52, wherein forming electrical connections from the first dice on the first substrate to the second dice on the second substrate includes routing a conductive trace from a first bond pad on an active device surface of the first substrate to a second bond pad on an active device surface of the second substrate through the through aperture.

54. The method of claim 52, wherein placing the first substrate on the adhesive includes placing a backside of the first substrate on the adhesive.

55. The method of claim 52, wherein forming electrical connections includes forming metal traces.

56. The method of claim 55, wherein forming metal traces includes forming a copper trace.

57. The method of claim 55, wherein forming metal traces includes forming an aluminum trace.

58. The method of claim 52, wherein singulating includes mechanically cutting the saw streets.

59. The method of claim 52, wherein mechanically cutting the saw streets includes partially cutting the electrical connection in the through apertures such that a portion of the electrical connection in a specific through aperture remains with each of the dice adjacent the through aperture.

60. A method, comprising:

providing a first substrate with a plurality of first dice separated by first saw streets;

providing a second substrate with a plurality of second dice separated by second saw streets;

applying an adhesive to a backside of the second substrate;

placing the first substrate on the adhesive such that the first saw streets align with the second saw streets;

curing the adhesive to fix the first substrate to the second substrate;

lazing the first saw street, the adhesive layer and the second saw street to form through holes;

forming electrical connections from the first dice on the first substrate to the second dice on the second substrate through the through holes; and

singulating aligned first and second dice from a remainder of the fixed first and second substrates.

61. The method of claim 60, wherein forming electrical connections includes forming metal traces including at least one metal from a group consisting essentially of copper and aluminum.

62. The method of claim 60, wherein lazing the first substrate, adhesive and second substrate includes excimer lazing the first substrate, the adhesive and the second substrate.

63. A method, comprising:

providing a first substrate with a plurality of first dice separated by first saw streets;

providing a second substrate with a plurality of second dice separated by second saw streets;

applying an adhesive to a backside of the second substrate;

placing the first substrate on the adhesive such that the first saw streets align with the second saw streets;

curing the adhesive to fix the first substrate to the second substrate;

cutting a kerf in the first saw streets of the first substrate through the first substrate;

removing the adhesive intermediate the plurality of first dice;

lazing the second saw street to form through holes;

forming electrical connections from the first dice on the first substrate to the second dice on the second substrate through the through holes; and

singulating aligned first and second dice from a remainder of the fixed first and second substrates.

65. The method of claim 63, wherein forming electrical connections includes forming a metal trace from a top surface bond pad of the first die to a top surface bond pad of the second die through the through hole.

66. The method of claim 63, wherein singulating the aligned first and second die includes mechanically cutting the aligned first and second saw streets.

67. The method of claim 66, wherein singulating the aligned fist and second die includes exposing the electrical connection along the side of the fixed first and second substrates.

64. The method of 63, wherein removing the adhesive intermediate the plurality of first dice includes chemically etching the adhesive.

68. A method of forming an integrated circuit (IC) package component, comprising:

fabricating a non-conductive base substrate having electrical conductors vertically extending from a top surface of the base substrate into the substrate and terminating within the base substrate, the top surface of the base substrate includes an interconnect area sized to receive an IC die; and

removing a portion of a bottom surface of the base substrate to expose the electrical conductors such that the electrical conductors are exposed on both the top and bottom surfaces of the base substrate.

69. The method of claim 68, further comprising:

attaching the IC die to the top surface of the base substrate; and

electrically connecting the IC die to the electrical conductors.

70. The method of claim 68, wherein removing the portion of the bottom surface of the base substrate is performed by either an etching operation or abrasive removal operation.