Translating device adapter having a common command set for interfacing multiple types of redundant storage devices to a host processor

• US 20040225775A1
• Filed: 03/01/2001
• Published: 11/11/2004
• Est. Priority Date: 03/01/2001
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Pellegrino, Greg, Tan, Choon Seng, Gunlock, Richard D., Curley, Matthew, Labarca, Erick
• Granted Patent: US 6,985,983 B2
• Time in Patent Office: Days
• US Class Current: 710/200
• CPC Class Codes: G06F 11/2069 Management of state, configuration or failover
• CPC Class Codes: G06F 11/2092 Techniques of failing over between control units
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

A translating host bus interface adapter is capable of connecting a computer system as a compute node to a storage area network. The adapter has a processor and a memory system containing firmware for execution in the processor. The host bus adapter is capable of recognizing first and second types of redundant storage accessible over the storage area network and translating generic storage commands into translated commands suitable for communicating with either type of redundant storage, and forwarding the translated commands onto the storage area network. The translating host bus adapter is also capable of constructing and maintaining a mirrored dataset comprising copies on redundant storage systems of either or both types.

Claims

1. A translating host bus interface adapter comprising:

an interface to a peripheral interconnect bus capable of interfacing the adapter to a computing system;

a host bus adapter processor and a host bus adapter memory system;

an interface to a storage area network;

firmware for execution in the host bus adapter processor, the firmware recorded in the host bus adapter memory system;

and wherein the host bus adapter is capable of recognizing a first type and a second type of redundant storage controller accessible over the interface to a storage area network, of receiving generic commands over the interface to a peripheral interconnect bus, translating these commands into translated commands suitable for communicating with a redundant storage controller of a type selected from the group consisting of the first type and the second type of redundant storage controller, and forwarding the translated commands onto the storage area network.

2. The host bus adapter of claim 1, wherein the host bus adapter is capable of concatenating a logical volume provided by a redundant storage controller of the first type with a logical volume provided by a redundant storage controller of the second type into a concatenated volume, and presenting the concatenated volume to the computing system.

3. The host bus adapter of claim 1, wherein the host bus adapter is capable of constructing and maintaining a mirrored dataset from a plurality of redundant storage controllers accessible over a storage area network, wherein the mirrored dataset comprises a first copy on at least a first redundant storage controller of the plurality of redundant storage controllers and a second copy on at least a second redundant storage controller of the plurality of redundant storage controllers.

4. The host bus adapter of claim 3, wherein the host bus adapter Is also capable of interfacing directly to at least one storage devic

5. The host bus adapt r of claim 3, wherein the first redundant storage controller and the second redundant storage controller are permitted to be of differing types.

6. The host bus adapter of claim 5, wherein the firmware is contained in electrically alterable memory of the memory system such that the firmware may be updated without removing the host bus adapter from the computing system.

7. The host bus adapter of claim 5, wherein the host bus adapter is capable of supporting multiple reply queues for use with a multiple processor computing system.

8. A method, comprising:

receiving, in a host bus adapter, a command from a host computer;

translating, in the host bus adapter, the command from a generic format in which the command was received into a first format adapted to be received by a first storage controller connected to the host bus adapter; and

forwarding the translated command to the first storage controller.

9. The method of claim 8, further comprising:

translating, in the host bus adapter, the command from a generic format in which the command was received into a second format adapted to be received by a second storage controller connected to the host bus adapter; and

forwarding the translated command to the second storage controller.

10. The method of claim 8, wherein receiving, in a host bus adapter, a command from a host computer comprises receiving a command header that comprises:

an address of a logical of a storage system or device; and

a reply queue identifier that designates a reply queue to which replies to the command are to be posted.

11. The method of claim 8, further comprising maintaining, in the host bus adapter a list of accessible logical units in a storage area network connected to the host bus adapter.

12. The method of claim 8, further comprising:

receiving, at the host bus adapter, a plurality of datasets from one or more storage controllers in response to a command from a host computer; and

combining, at the host bus adapter, the plurality of datasets into a combined dataset.

13. The method of claim 8, further comprising;

detecting a failure condition associated with a first storage controller connected to the host bus adapter; and

re-routing one or more commands addressed to the first storage controller to a second storage controller connected to the host bus adapter.

14. A host bus adapter, comprising:

an interface to a host computer system;

a processor and a memory system;

an interface to a storage area network; and

logic instructions stored in the memory system which, when executed by the processor, configure the processor to;

recognize a first type and a second type of redundant storage controller accessible over the interface to a storage area network;

receive a generic command from the host computer system;

translate the generic command into translated commands suitable for communicating with a redundant storage controller of a type selected from the group consisting of the first type and the second type of redundant storage controller, and forward the translated commands onto the storage area network.

15. The host bus adapter of claim 14, further comprising logic instructions which, when executed by the processor, configure the processor to concatenate a logical volume provided by a redundant storage controller of the first type with a logical volume provided by a redundant storage controller of the second type into a concatenated volume, and present the concatenated volume to the host computer system.

16. The host bus adapter of claim 14, further comprising logic instructions which, when executed by the processor, configure the processor to construct and maintain a mirrored dataset from a plurality of redundant storage controllers accessible over a storage area network, wherein the mirrored dataset comprises a first copy on at least a first redundant storage controller of the plurality of redundant storage controllers and a second copy on at least a second redundant storage controller of the plurality of redundant storage controllers.

17. The host bus adapter of claim 14, wherein the logic instruction are embodied in firmware contained in electrically alterable memory of the memory system such that the firmware may be updated without removing the host bus adapter from the computing system.

18. The host bus adapter of claim 14, further comprising logic instructions which, when executed by the processor. enable the processor to support multiple reply queues for use with a multiple processor computing System.