Integated circuit devices having active regions with expanded effective widths

• US 20040227208A1
• Filed: 06/14/2004
• Published: 11/18/2004
• Est. Priority Date: 10/28/2000
• Status: Active Grant

• Current Assignee: Jong-Woo Park, Kang-Yoon Lee
• Original Assignee: Jong-Woo Park, Kang-Yoon Lee
• Inventors: Lee, Kang-yoon, Park, Jong-woo
• Granted Patent: US 7,187,032 B2
• Time in Patent Office: Days
• US Class Current: 257/510
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

An integrated circuit device includes a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench.

Claims

1. An integrated circuit device, comprising:

a substrate having a trench formed therein;

an isolation layer disposed in the trench so as to cover a first sidewall portion of the trench; and

a gate electrode disposed on a second sidewall portion of the trench.

2. The integrated circuit device of claim 1, further comprising:

a gate insulating layer disposed between the gate electrode and the second sidewall portion of the trench.

3. The integrated circuit device of claim 1, further comprising:

a buffer layer disposed between the isolation layer and the trench.

4. The integrated circuit device of claim 3, wherein the buffer layer comprises silicon oxide.

5. The integrated circuit device of claim 3, further comprising:

a liner layer disposed between the isolation layer and the buffer layer.

6. The integrated circuit device of claim 1, wherein the second sidewall portion of the trench comprises an impurity layer.

7. The integrated circuit device of claim 6, wherein the impurity layer comprises boron dopant.

8. The integrated circuit device of claim 1, wherein the substrate has a mesa formed thereon adjacent the trench that has an upper surface that intersects the second sidewall portion of the trench, and wherein a length of the second sidewall portion of the trench is at least 15% of a length of the upper surface.

9. The integrated circuit device of claim 8, wherein the length of the second sidewall portion of the trench is approximately 30%-60% of the length of the upper surface.

10-21. -21. (Canceled)

22. An integrated circuit device, comprising:

a substrate having a mesa structure thereon, the mesa structure having sidewalls and a top surface; and

a gate electrode on the mesa structure that extends across the top surface and down a portion of at least one of the sidewalls.

23. The integrated circuit device of claim 22, further comprising:

a gate insulating layer disposed between the gate electrode and the portion of at least one of the sidewalls.

24. The integrated circuit device of claim 22, wherein the portion of at least one of the sidewalls is a first portion of at least one of the sidewalls, the integrated circuitd device further comprising:

an isolation layer disposed on a second portion of at least one of the sidewalls.

25. A semiconductor device comprising:

a semiconductor substrate;

a trench which is formed by selectively etching the semiconductor substrate and which is partially filled with an isolation layer such that the upper sidewalls of the trench are exposed;

a gate insulating layer which is formed on upper sidewalls of the exposed trench and an upper surface of the semiconductor substrate; and

a gate electrode which is formed on the gate insulating layer.

26. The semiconductor device of claim 25, further comprising a buffer layer which is formed at the interface between the isolation layer and the bottom and sidewall of the trench.

27. The semiconductor device of claim 26, further comprising a liner of a silicon nitride layer which is formed at the interface between the buffer layer and the isolation layer.

28. The semiconductor device of claim 25, wherein the surface of the isolation layer is lower than the upper surface of the semiconductor substrate.

29. The semiconductor device of claim 25, further comprising an impurity layer for controlling threshold voltage which is formed under the surface of the upper sidewalls of the trench and the upper surface of the semiconductor substrate.

30. The semiconductor device of claim 25, wherein the gate electrode covers the upper sidewalls of the trench and the surface of the isolation layer and is formed on the gate insulating layer which is interposed between the gate electrode and the upper surface of the semiconductor substrate.

31-39. -39. (Canceled)