Level translator circuit for power supply disablement

• US 20040227541A1
• Filed: 05/16/2003
• Published: 11/18/2004
• Est. Priority Date: 05/16/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Correale, Anthony Jr.
• Granted Patent: US 6,861,873 B2
• Time in Patent Office: Days
• US Class Current: 326/80
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A level translator circuit for use between a transmitting voltage potential circuit and a receiving voltage potential circuit is disclosed. The translator circuit comprises a logic element coupled between the transmitting circuit and the receiving circuit for translating the voltage level. The logic element includes a device which has a threshold voltage of such a level that leakage current will be minimized when the transmitting voltage potential circuit'"'"'s power supply is disabled. In one embodiment, the logic element comprises a multistage inverter wherein a first stage comprises an intermediate power supply. The intermediate power supply allows for the threshold voltage to be lower. Accordingly, a level translation circuit is provided that operates effectively even when one of the voltage potential circuits is turned off. In addition, leakage current is minimized for two distinct power supplies by providing a high threshold voltage device within the level translator of the circuit to ensure that an appropriate logical level is provided at the output of the circuit.

Claims

1. A level translator circuit for use between a transmitting voltage potential circuit and a receiving voltage potential circuit;

the translator circuit comprising;

a logic element coupled between the transmitting circuit and the receiving circuit for translating the voltage level, wherein the logic element includes a device which has a threshold voltage of such a level that leakage current will be minimized when the transmitting voltage potential circuit'"'"'s power supply is disabled.

2. The level translator circuit of claim 1 wherein the transmitting voltage potential circuit comprises a lower voltage potential circuit and the receiving voltage potential circuit comprises a higher voltage potential circuit.

3. The level translator circuit of claim 1 wherein the logic element comprises an inverter.

4. The level translator circuit of claim 1 wherein the inverter comprises:

an nfet transistor coupled to the receiving circuit and the transmitting circuit; and

a pfet transistor coupled to the nfet transistor, the receiving circuit and the transmitting circuit, wherein the pfet transistor is a high threshold device.

5. The level translator circuit of claim 1 wherein the logic element comprises a multi-stage inverter.

6. The level translator of claim 5 wherein the first stage of the multi-stage inverter includes an intermediate power supply

7. A level translator circuit for use between a transmitting voltage potential circuit and a receiving voltage potential circuit;

the translator circuit comprising;

a first transistor coupled to the transmitting voltage potential circuit, wherein the first transistor comprises a high threshold device;

a clamping mechanism coupled to the first transistor;

a second transistor coupled to the first transistor, a higher voltage potential and the receiving voltage potential circuit;

a third transistor coupled to the receiving voltage potential circuit, the higher voltage potential and the second transistor; and

a fourth transistor coupled to the transmitting voltage potential circuit, the receiving voltage potential circuit, and to a ground potential, wherein the clamping mechanism clamps a control node of the translator circuit such that an appropriate logic level is provided to the receiving voltage potential circuit, wherein the high threshold device has a threshold voltage of such a level that leakage current will be minimized when the transmitting voltage potential circuit'"'"'s power supply is disabled.

8. The level translator circuit of claim 7 wherein the transmitting voltage potential circuit comprises a lower voltage potential circuit and the receiving voltage potential circuit comprises a higher voltage potential circuit.

9. The level translator circuit of claim 7 wherein the clamping mechanism device is coupled to a gate of the first transistor.

10. The level translator circuit of claim 7 wherein the first and fourth transistors comprise nfet transistors and the second and third transistors comprise pfet transistors.

11. The level translator of claim 9 wherein the high threshold device comprises an nfet transistor.