Variable refresh control for a memory

• US 20040233706A1
• Filed: 06/28/2004
• Published: 11/25/2004
• Est. Priority Date: 02/19/2003
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: John M. Burgan
• Inventors: Burgan, John M.
• Granted Patent: US 6,862,240 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 29/50016 of retention

Abstract

A memory (10) includes a variable refresh control circuit (20) for controlling the refresh rate of a memory array (12) using a capacitor for data storage. In one embodiment, each test cell of a plurality of test memory cells (30, 32, 34, and 36) is refreshed at different rates. A monitor circuit (18) is provided for monitoring the stored logic state of each of the plurality of test memory cells, and in response, adjusting the refresh rate of the memory array (12). In another embodiment, a variable refresh control circuit (20′) includes a plurality of test memory cells (70, 72, 74, and 76) that are all refreshed at the same rate but each of the test memory cells (70, 72, 74, and 76) is implemented to have a different charge storage capacity than the other test memory cells. The monitor circuit (18) monitors the stored logic state of each of the plurality of test memory cells (70, 72, 74, and 76), and in response, adjusts a refresh rate of the memory array (12).

Claims

1. (Canceled)

2. (Canceled)

3. (Canceled)

4. (Canceled)

5. (Canceled)

6. (Canceled)

7. (Canceled)

8. (Canceled)

9. A memory comprising:

a plurality of memory cells that require periodic refreshing to maintain stored data;

a variable refresh control circuit comprising a plurality of test memory cells, each of the plurality of test memory cells including a capacitor for storing charge representative of a stored logic state, the plurality of test memory cells being refreshed at a predetermined refresh rate, and each of the plurality of test memory cells being implemented to store a different amount of charge than other test memory cells of the plurality of test memory cells; and

a monitor circuit for monitoring the stored logic state of each of the plurality of test memory cells, and in response, adjusting a refresh rate of the plurality of memory cells.

10. The memory of claim 9 wherein a charge storage ability of one test cell of the plurality of test memory cells is greater than a charge storage ability of each of the plurality of memory cells for the predetermined refresh rate.

11. The memory of claim 9, wherein the plurality of memory cells and the plurality of test memory cells are dynamic random access memory (DRAM) cells.

12. The memory of claim 9, further comprising a sense amplifier coupled to a first test cell of the plurality of test memory cells, the first test cell having a charge storage ability that is greater than a charge storage ability of one of the plurality of memory cells, the sense amplifier providing a signal for indicating if the predetermined refresh rate is sufficient for reliably maintaining a stored logic state of the first test cell.

13. The memory of claim 12, wherein if the predetermined refresh rate is not sufficient for reliably maintaining the stored logic state of the first test cell, increasing the refresh rate of the plurality of memory cells.

14. The memory of claim 9, wherein the plurality of test memory cells are organized as pairs of test memory cells, wherein a pair of test memory cells includes a first test cell and a second test cell, the first test cell for storing a high logic state and the second test cell for storing a low logic state, the each test cell of the pair of test memory cells having a charge leakage rate that is greater than a charge leakage rate of one of the plurality of memory cells.

15. The memory of claim 9, wherein the plurality of test memory cells include a first test cell and a second test cell, the first test cell having a first charge storage ability that is greater than a charge storage ability of one of the plurality of memory cells, the second test cell having a second charge storage ability that is greater than the first charge storage ability.

16. The memory of claim 9, wherein the plurality of test memory cells and the plurality of memory cells are implemented together on a single integrated circuit.

17. (Canceled)

18. A method for refreshing a memory array having a plurality of memory cells for storing data, comprising the steps of:

providing a plurality of test memory cells, each of the plurality of test memory cells being implemented to have different charge storage ability than other test memory cells of the plurality of test memory cells;

refreshing the test memory cells at a predetermined refresh rate;

monitoring the charge storage ability of the plurality of test memory cells; and

adjusting the refresh rate of the memory array in response to the monitoring of the charge storage ability of the plurality of test memory cells.

19. The method of claim 18, where the step of monitoring the charge storage ability of the plurality of test memory cells further comprises monitoring the ability of the plurality of test memory cells to maintain a predetermined minimum voltage maginitude.