System and method for detecting defects in a thin-film-transistor array

• US 20040246015A1
• Filed: 06/06/2003
• Published: 12/09/2004
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Yieldboost Technologies Incorporated
• Original Assignee: Yieldboost Technologies Incorporated
• Inventors: Chung, Kyo Young
• Granted Patent: US 7,053,645 B2
• Time in Patent Office: Days
• US Class Current: 324/764
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: H04N 17/04 for receivers

Abstract

A system and method for detecting a defect in a transistor array includes applying a test signal to the array, monitoring pixel voltages along a gate line of the array, and detecting a defect associated with the gate line based on a variation in the pixel voltages along the gate line during the monitoring step. The system and method can also detect a precise location of the defect based on a rate of change in the variation of the pixel voltages along the gate line.

Claims

1. A method for detecting a defect in a transistor array, comprising:

applying a test signal to the array;

monitoring pixel voltages at different monitoring points along a gate line of the array; and

detecting a defect associated with the gate line based on how the pixel voltages vary from one monitoring point to another monitoring point during said monitoring step.

2. The method of claim 1, wherein the defect is a short between the gate line and a common line of the array.

3. The method of claim 2, wherein the common line and the gate line are connected to a same transistor element in the array.

4. The method of claim 2, wherein the common line and the gate line are connected to different transistor elements in the array.

5. The method of claim 1 further comprising:

detecting a location of the defect based on a change in slope of a profile of the pixel voltages.

6. The method of claim 1 further comprising:

detecting a location of the defect based on a rate of change in the variation of the pixel voltages along the gate line.

7. The method of claim 6, wherein the location of the defect corresponds to a point along the gate line where the variation changes from increasing pixel voltages to decreasing pixel voltages.

8. The method of claim 6, wherein the location of the defect corresponds to a point along the gate line where the variation changes from decreasing pixel voltages to increasing pixel voltages.

9. The method of claim 1, further comprising:

detecting a location of the defect based on one of a minimum value or a maximum value on a pixel voltage profile.

10. The method of claim 1, wherein the transistor array is a TFT array.

11. A system for detecting a defect in a transistor array, comprising:

a signal generator which applies a test signal pattern to the array; and

a detector which detects a defect in the array based on how pixel voltages vary between monitoring points along an array gate line.

12. The system of claim 11 wherein the defect is a short between the gate line and a common line of the array.

13. The system of claim 12 wherein the common line and the gate line are connected to a same transistor element in the array.

14. The system of claim 12 wherein the common line and the gate line are connected to different transistor elements in the array.

15. The system of claim 11 wherein the detector detects a location of the defect based on a change in slope of a profile of the pixel voltages.

16. The system of claim 11 wherein the detector detects a location of the defect based on a rate of change in the variation of the pixel voltages along the gate line.

17. The system of claim 16 wherein the location of the defect corresponds to a point along the gate line where the variation changes from increasing pixel voltages to decreasing pixel voltages.

18. The system of claim 16, wherein the location of the defect corresponds to a point along the gate line where the variation changes from decreasing pixel voltages to increasing pixel voltages.

19. The system of claim 11, wherein the transistor array is a TFT array.

20. A signal analyzer for testing a TFT array, comprising:

at least one electrode for inputting a test signal into the TFT array; and

a processor which monitors how pixel voltages vary between monitoring points along a gate line of the array, and detects a defect associated with the gate line based on the variation.

21. The signal analyzer of claim 20, wherein the defect is a short between the gate line and a common line of the array.

22. The signal analyzer of claim 21, wherein the common line and the gate line are connected to a same transistor element in the array.

23. The signal analyzer of claim 21, wherein the common line and the gate line are connected to different transistor elements in the array.

24. The signal analyzer of claim 20, wherein the processor detects a location of the defect based on a change in slope of a profile of the pixel voltages.

25. The signal analyzer of claim 20, wherein the processor detects a location of the defect based on a rate of change in the variation of the pixel voltages along the gate line.

26. The signal analyzer of claim 25, wherein the location of the defect corresponds to point along the gate line where the variation changes from increasing pixel voltages to decreasing pixel voltages.

27. The signal analyzer of claim 25, wherein the location of the defect corresponds to point along the gate line where the variation changes from decreasing pixel voltages to increasing pixel voltages.

28. The signal analyzer of claim 20, wherein the transistor array is a TFT array.