Configurable real-time trace port for embedded processors

  • US 20040250164A1
  • Filed: 05/22/2003
  • Published: 12/09/2004
  • Est. Priority Date: 05/22/2003
  • Status: Active Grant
First Claim
Patent Images

1. An embedded processor comprising:

  • a processor core for executing a program instruction associated with an instruction word transmitted on an instruction bus, and for transmitting a corresponding data word on a data bus in response to the executed program instruction; and

    a trace port circuit including;

    a configurable filter circuit coupled to the instruction bus and the data bus for selectively passing at least a portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word satisfies a user-defined trigger event;

    a compression circuit for compressing said at least one of the instruction word and the corresponding data word passed from the configurable filter circuit; and

    an output buffer for temporarily storing the compressed instruction word and compressed data word.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×