Configurable real-time trace port for embedded processors

• US 20040250164A1
• Filed: 05/22/2003
• Published: 12/09/2004
• Est. Priority Date: 05/22/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG)
• Inventors: Ober, Robert E., Ahmad, Sagheer
• Granted Patent: US 7,149,926 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G06F 11/364 tracing values on a bus
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

An embedded processor having a programmable trace port that selectively limits the amount of trace information passed from the processor core to an output buffer, and selectively controls the rate at which the trace information is output from the output buffer to an off-chip debug system. A configurable on-chip filter circuit selectively passes data and program information based on a wide range of user-defined combinations and/or sequences of trigger events (e.g., instruction addresses/types or data addresses/values). The filtered trace information is then compressed using separate data and program compression circuits, and passed to separate data and program output buffer. The data output buffer includes an adjustable read (output) rate (e.g., one-half or one-quarter of the processor core clock cycle), and allows a user to select between one or two output pointers.

Claims

1. An embedded processor comprising:

a processor core for executing a program instruction associated with an instruction word transmitted on an instruction bus, and for transmitting a corresponding data word on a data bus in response to the executed program instruction; and

a trace port circuit including;

a configurable filter circuit coupled to the instruction bus and the data bus for selectively passing at least a portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word satisfies a user-defined trigger event;

a compression circuit for compressing said at least one of the instruction word and the corresponding data word passed from the configurable filter circuit; and

an output buffer for temporarily storing the compressed instruction word and compressed data word.

2. The embedded processor according to claim 1,

wherein the configurable filer circuit includes a first trace filter including a switch having input terminals connected to the instruction bus and the data bus, and

wherein the embedded processor further comprises a on-chip debug support (OCDS) circuit coupled to the instruction bus and the data bus, the OCDS circuit including means for storing instruction information and data information, and means for generating a switch control signal that causes the first switch to pass said portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word matches the stored instruction information and data information.

3. The embedded processor according to claim 2, wherein the OCDS circuit comprises:

programmable trigger generator including;

a plurality of trigger event detection registers, each said register including a memory circuit for storing at least one trigger value, and means for asserting a pre-trigger signal only when the stored trigger value matches a corresponding value transmitted on at least one of the data address bus, the data value bus, and the instruction bus, and

a programmable trigger logic circuit including a function generator for generating an intermediate trigger signal in response to a user-defined combination of the pre-trigger signals generated by the plurality of trigger event detection registers; and

an action generator circuit for asserting a BWP trigger in response to the intermediate trigger signal.

4. The embedded processor according to claim 3, wherein the plurality of trigger event detection registers include an instruction register for storing a first instruction address and a second instruction address, and wherein the instruction register includes means for asserting a first pre-trigger signal when a third instruction address transmitted on the instruction address bus is within a range defined by the first and second instruction addresses.

5. The embedded processor according to claim 3, wherein the plurality of trigger event detection registers include a data register for storing a first data address, a second data address, and wherein the data register includes means for asserting a second pre-trigger signal when a third data address transmitted on the data address bus is within a range defined by the first and second data addresses.

6. The embedded processor according to claim 5, wherein the data register further comprises a first data value and a mask value for masking a portion of the first data value, and wherein the data register includes means for asserting the second pre-trigger signal when a second data value transmitted on the data value bus matches an unmasked portion of the first data value.

7. The embedded processor according to claim 3, wherein the function generator comprises a sum-of-products circuit for generating a combinational trigger signal that represents a user-defined function of the plurality of pre-trigger signals generated by the plurality of trigger event detection registers.

8. The embedded processor according to claim 7, wherein the sum-of-products circuit comprises sixteen registers and a multiplexing structure that is controlled by four pre-trigger signals to pass a data value from one of the sixteen registers to an output terminal of the multiplexing structure.

9. The embedded processor according to claim 3, wherein the programmable trigger logic circuit comprises first, second, third, and fourth function generators, each of the first, second, third, and fourth function generators including means for generating an associated intermediate trigger signal in response to a user-defined combination of the pre-trigger signals.

10. The embedded processor according to claim 9, wherein the programmable trigger logic circuit further comprises a programmable state machine coupled to receive the associated intermediate trigger signals generated by the first, second, third, and fourth function generators, wherein the programmable state machine includes means for generating a state trigger signal when said associated intermediate trigger signals are asserted in a predefined sequence.

11. The embedded processor according to claim 10, wherein the programmable state machine comprises a four-state finite state machine that includes means for passing control from a first state to a second state when a stored value associated with the first state matches an asserted one of said intermediate trigger signals.

12. The embedded processor according to claim 2,

wherein the configurable filter circuit further includes a first trace filter having a first switch connected between a first intermediate bus and a first output bus, a second switch connected between a second intermediate bus and a second output bus, and third switch connected between a third intermediate bus and a third output bus, wherein the first, second and third intermediate busses are connected to corresponding output terminals of the first trace filter, and

wherein the first, second and third output busses are connected to the compression circuit.

13. The embedded processor according to claim 12, wherein the compression circuit comprises a program compression circuit connected to the first output bus, and a data compression circuit connected to the second and third output busses.

14. The embedded processor according to claim 13, wherein the output buffer comprises a first First-In-First-Out (FIFO) circuit coupled to the program compression circuit, and a second FIFO circuit coupled to the data compression circuit.

15. The embedded processor according to claim 1, wherein the compression circuit comprises:

means for converting the instruction word into at least one program trace bytes according to a predetermined compression scheme, and for transmitting the at least one program trace bytes to the output buffer; and

means for generating a plurality of identification codes, each identification code being transmitted with a corresponding program trace byte.

16. The embedded processor according to claim 15, wherein the output buffer comprises a first First-In-First-Out (FIFO) circuit including:

a plurality of sequentially arranged registers;

a write pointer circuit for sequentially writing the at least one program trace bytes into the sequentially arranged registers at a processor core frequency; and

a read pointer/driver circuit for sequentially reading program trace bytes from the sequentially arranged registers at a user-defined frequency, and for driving the read program trace bytes onto a first set of device pins.

17. The embedded processor according to claim 16, further comprising means for adjusting the user-defined frequency between f/2 and f/4, where f is the processor core frequency.

18. The embedded processor according to claim 16, further comprising means for detecting an over-run condition of the first FIFO circuit, for erasing program trace bytes from the plurality of sequentially arranged registers, and for writing an error code into a selected register of the plurality of sequentially arranged registers.

19. The embedded processor according to claim 1,

wherein each data word includes a data address transmitted on a first portion of the data bus, and a data value transmitted on a second portion of the data bus, and

wherein the compression circuit comprises:

means for converting the data value and the data address into at least one data trace words according to a predetermined compression scheme, and for transmitting the at least one data trace words to the output buffer; and

means for generating at least one identification codes, each identification code being transmitted with a corresponding data trace word.

20. The embedded processor according to claim 19, wherein the output buffer comprises a second First-In-First-Out (FIFO) circuit including:

a plurality of sequentially arranged registers;

a write pointer circuit for sequentially writing the at least one data trace words into the sequentially arranged registers at a processor core frequency; and

a read pointer/driver circuit for sequentially reading data trace words from the sequentially arranged registers at a user-defined frequency, and for driving the read program trace bytes onto a second set of device pins.

21. The embedded processor according to claim 20, further comprising means for adjusting the user-defined frequency between f/2 and f/4, where f is the processor core frequency.

22. The embedded processor according to claim 20, wherein the read pointer circuit further comprising means for adjusting between a first control state in which one data trace word is read and driven onto the second set of device pins during each clock cycle of the user-defined frequency, and a second control state in which a first data trace word is read from a first register and driven onto the second set of device pins, and a second data trace word is read from a second register and driven onto the third set of device pins during each clock cycle of the user-defined frequency.

23. The embedded processor according to claim 20, further comprising means for detecting an over-run condition of the second FIFO circuit, for erasing program trace bytes from the plurality of sequentially arranged registers, and for writing an error code into a selected register of the plurality of sequentially arranged registers.