Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material

• US 20040256699A1
• Filed: 04/01/2004
• Published: 12/23/2004
• Est. Priority Date: 04/01/2003
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Bensahel, Daniel, Campidelli, Yves, Kermarrec, Olivier, Morand, Yves, Cosnier, Vincent
• Granted Patent: US 7,129,563 B2
• Time in Patent Office: Days
• US Class Current: 257/616
• CPC Class Codes: H01L 21/2807 the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si_1-xGe_x, where 0.5<x<1, at a temperature substantially below the temperature at which a poly-Si is deposited by thermal chemical vapor deposition (CVD).

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a gate dielectric made of high dielectric permittivity material;

depositing, directly on the gate dielectric, a Si_1-x,Ge_x first layer, where 0.5<

x<

1, at a temperature substantially below the temperature at which the poly-Si is deposited by thermal chemical vapor deposition (CVD); and

depositing a Si_1-yGe_y second layer, where 0<

y<

1, on top of the Si_1-xGe_x first layer.

2. The method of claim 1, wherein the Si_1-xGe_x first layer is deposited by thermal CVD.

3. The method of claim 1, wherein at least one of the Si_1-xGe_x first layer and the Si_1-yGe_y second layer is predominantly Ge.

4. The method of claim 1, wherein 0.7<

x<

1.

5. The method of claim 1, wherein x=1.

6. The method of claim 1, wherein 0.7<

x<

1 and 0.7<

y<

1.

7. The method of claim 6, wherein x=y=1.

8. The method of claim 1, wherein the Si_1-xGe_x first layer is doped in situ so that doping in is in a presence of dopants in a gas mixture used to deposit the Si_1-xGe_x first layer.

9. The method of claim 1, wherein the Si_1-yGe_y second layer is doped in situ so that doping in is in a presence of dopants in a gas mixture used to deposit the Si_1-yGe_y second layer.

10. The method of claim 1, further comprising:

diffusion annealing so that at least one of Ge and Si diffuse betweenthe Si_1-xGe_x first layer iand the Si_1-y Ge_y second layer.

11. The method of claim 1, wherein the gate dielectric is selected in a group of metal oxides consisting of HfO₂, ZrO₂, HfSiO and ZrSiO.

12. A semiconductor device comprising:

a substrate;

a gate dielectric deposited on the substrate, wherein the gate dielectric is made of high dielectric permittivity material; and

a gate formed on top of a Si_1-xGe_x first layer comprising;

a Si_1-xGe_x first layer formed directly on the gate dielectric, where 0.5<

x<

1; and

,

a Si_1-yGe_y second layer, formed on top of the Si_1-xGe_x first layer where 0<

y<

1.

13. The semiconductor device of claim 12, wherein at least one of the Si_1-xGe_x first layer and the Si_1-yGe_y second layer is predominantly Ge.

14. The semiconductor device of claim 12, wherein the gate further comprises a layer for limiting the diffusion of at least one of Ge and Si between the Si_1-yGe_y second layer and the Si_1-xGe_x first layer.

15. The semiconductor device of claim 12, wherein the gate dielectric is selected in a group of metal oxides consisting of HfO₂, ZrO₂, HfSiO and ZrSiO.

16. The semiconductor device of claim 12, wherein x=1.

17. The semiconductor device of claim 12, wherein x=y=1.

18. The semiconductor device of claim 12, wherein an interface between the gate dielectric and the gate is predominantiy made of Si.