Battery cell monitoring and balancing circuit

• US 20040257042A1
• Filed: 06/19/2003
• Published: 12/23/2004
• Est. Priority Date: 06/19/2003
• Status: Active Grant

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: Li, Guoxing, Liu, Liusheng
• Granted Patent: US 7,081,737 B2
• Time in Patent Office: Days
• US Class Current: 320/130
• CPC Class Codes: H01M 10/441 for several batteries or cells simultaneously or sequentially
• CPC Class Codes: H02J 7/0018 using separate charge circuits
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A monitoring circuit for accurately monitoring a voltage level from each of a plurality of battery cells of a battery pack includes an analog to digital converter (ADC) and a processor. The ADC is configured to accept an analog voltage signal from each of the plurality of battery cells and convert each analog voltage signal to a digital signal representative of an accurate voltage level of each battery cell. The processor receives such signals and provides a safety alert signal based on at least one of the signals. The ADC resolution may be adjustable. A balancing circuit provides a balancing signal if at least two of the digital signals indicate a voltage difference between two cells is greater than a battery cell balance threshold. An electronic device including such monitoring and balancing circuits is also provided. Various methods are also provided.

Claims

1. A monitoring circuit for accurately monitoring a voltage level from each of a plurality of battery cells of a battery pack, said monitoring circuit comprising:

an analog to digital converter (ADC) configured to accept an analog voltage signal from each of said plurality of battery cells and convert each said analog voltage signal to a digital signal representative of a voltage level of each said battery cell; and

a processor configured to receive each said digital signal and to provide a safety alert signal based on at least one of said digital signals.

2. The monitoring circuit of claim 1, wherein said safety alert signal is a charging alert signal if at least one of said digital signals is representative of a voltage level of one of said battery cells greater than an over voltage threshold value during a predetermined monitoring time interval while said battery pack is being charged.

3. The monitoring circuit of claim 2, wherein said charging alert signal is provided if one of said digital signals is representative of a voltage level of one of said battery cells greater than said over voltage threshold value while said battery pack is being charged.

4. The monitoring circuit of claim 2, wherein said over voltage threshold level is adjustable by said processor.

5. The monitoring circuit of claim 4, wherein said over voltage threshold level is adjustable by said processor based on ambient temperature.

6. The monitoring circuit of claim 1, wherein said safety alert signal is a discharge alert signal if at least one of said digital signals is representative of a voltage level of one of said battery cells less than an under voltage threshold value during a predetermined monitoring time interval while said battery pack is being discharged.

7. The monitoring circuit of claim 6, wherein said discharge alert control signal is provided if one of said digital signals is representative of a voltage level of one of said battery cells less than said under voltage threshold value while said battery pack is being discharged.

8. The monitoring circuit of claim 6, wherein said under voltage threshold level is adjustable by said processor.

9. The monitoring circuit of claim 8, wherein said under voltage threshold level is adjustable by said processor based on ambient temperature.

10. The monitoring circuit of claim 1, wherein said ADC is an averaging type ADC.

12. The monitoring circuit of claim 1, wherein said ADC has a resolution, and said resolution is adjustable by said processor.

13. The monitoring circuit of claim 1, further comprising:

a switch network coupled between said battery pack and said ADC, said switch network having a plurality of switches controlled by said processor, said switch network enabling each of said plurality of battery cells to be directly coupled to said ADC through said switch network.

14. The monitoring circuit of claim 1, wherein said ADC has a positive input terminal and a negative input terminal, wherein a first offset value for a first battery cell is determined by coupling one terminal of said first battery cell to both said positive and said negative input terminals of said ADC, wherein said processor is further configured to apply said first offset value to a first digital signal representative of a voltage level of said first battery cell thereby providing a first calibrated digital signal.

15. The monitoring circuit of claim 14, wherein a second offset value for a second battery cell is determined by coupling one terminal of said second battery cell to both said positive and said negative input terminals of said ADC, wherein said processor is further configured to apply said second offset value to a second digital signal representative of a voltage level of said second battery cell thereby providing a second calibrated digital signal.

16. The monitoring circuit of claim 1, wherein said ADC samples a voltage level of each said battery cell once every sampling time period, wherein said sampling time period is adjustable by said processor.

17. The monitoring circuit of claim 16, wherein said sampling time period has a first time interval during a first condition, and said sampling time period has a second time interval during a second condition, said second time interval being longer than said first time interval and said second condition being a sleep mode of said battery pack.

18. The monitoring circuit of claim 6, wherein said safety alert signal is a first discharge alert signal if at least one of said digital signals is representative of a voltage level of one of said battery cells less than a first under voltage threshold level during said predetermined monitoring time interval while said battery pack is being discharged, wherein said first under voltage threshold level is greater than said under voltage threshold level.

19. The monitoring circuit of claim 18, wherein said safety alert signal is a second discharge alert signal if at least one of said digital signals is representative of a voltage level of one of said battery cells less than a second under voltage level during said predetermined monitoring time interval while said battery pack is being discharged, wherein said second under voltage threshold level is less than first under voltage threshold level and greater than said under voltage threshold level.

20. The monitoring circuit of claim 1, further comprising:

a protection circuit configured to compare a signal representative of a current level associated with said battery pack to an over current threshold and to provide an over current alert signal to said processor if said current level is greater than said over current threshold.

21. The monitoring circuit of claim 20, wherein said protection circuit is further configured to compare a signal representative of said current level associated with said battery pack to a short circuit current threshold and to provide a short circuit current alert signal to said processor if said current level is greater than said short circuit current threshold.

11. The monitoring circuit of claim 11, wherein said averaging type ADC samples a voltage level for each battery cell a plurality of times over a sampling period before converting said analog voltage signal to an associated digital signal.

22. A balancing circuit comprising:

an analog to digital converter (ADC) configured to accept an analog voltage signal from each of a plurality of battery cells of a battery pack and convert each said analog voltage signal to a digital signal representative of a voltage level of each said battery cell; and

a processor configured to receive each said digital signal and to provide a balance signal if at least two of said digital signals are representative of a voltage difference between a first voltage level of a first battery cell and a second voltage level of a second battery cell greater than a battery cell balance threshold.

23. The balancing circuit of claim 22, further comprising:

a bleeding network circuit configured to accept said balance signal and provide a bleeding current to any one of said plurality of battery cells in response to said balance signal.

24. The balancing circuit of claim 23, wherein said bleeding network circuit provides a first bleeding current to said second battery cell if said second voltage level of said second battery cell is greater than said first voltage level of said first battery cell, said bleeding network circuit applying said first bleeding current for a first time interval to reduce said second voltage level to a level substantially equal to said first voltage level.

25. The balancing of claim 24, wherein a third battery cell has a third voltage level, said third voltage level greater than said first voltage level, said third voltage level greater than said second voltage level, said bleeding network circuit applying said first bleeding current to said third battery cell for a second time interval to reduce said third voltage level to said level substantially equal to said first voltage level, wherein at least some portion of said first time interval and said second time interval overlap.

26. The balancing of claim 25, wherein said first time interval has a first starting time and said second time interval has a second starting time, said first starting time substantially equal to said second starting time and wherein said second time interval is longer than said first time interval.

27. The balancing circuit of claim 23, wherein said bleeding current provided by said bleeding network circuit is adjustable in response to said balance signal from said processor.

28. The balancing circuit of claim 27, wherein a third battery cell has a third voltage level, and wherein said second voltage level is greater than said first voltage level by a first difference level, and said third voltage level is greater than said first voltage level by a second difference level, and wherein said second difference level is greater than said first difference level, and wherein said bleeding network circuit provides a first bleeding current to said second battery cell and a second bleeding current to said third battery cell, said second bleeding current greater than said first bleeding current.

29. The balancing circuit of claim 27, wherein said bleeding network circuit comprises a plurality of bleeding circuits associated with each said plurality of battery cells, at least one of said plurality of bleeding circuits comprising:

a first switch having a first resistive element coupled to a terminal of said first switch, said first resistive element having a first resistive value; and

a second switch having a second resistive element coupled to a terminal of said second switch, said second resistive element having a second resistive value, said second resistive value less than said first resistive value.

30. The balancing circuit of claim 29, wherein a first bleeding current is applied to an associated battery cell if said first switch is ON and said second switch is OFF, and a second bleeding current is applied to said associated battery cell if said first switch if OFF and said second switch if ON, wherein said second bleeding current is greater than said first bleeding current.

31. The balancing circuit of claim 22, wherein said balance signal is provided to a charge shuttling circuit configured to shuttle charges among said plurality of battery cells in response to said balance signal.

32. The balancing circuit of claim 31, wherein said charge shuttling circuit is configured to shuttle charges from said second battery cell to said first battery cell if said second voltage level is greater than said first voltage level.

33. The balancing circuit of claim 31, wherein said charge shuttling circuit comprises an energy storage element.

34. The balancing circuit of claim 33, wherein said energy storage element comprises a capacitor.

35. The balancing circuit of claim 33, further comprising:

a switch network coupled between said battery pack and said ADC, said processor controlling said switch network to couple said second battery cell to said energy storage element to transfer a charge from said second battery cell to said energy storage element, said processor controlling said switch network to couple said first battery cell to said energy storage element to transfer said charge from said energy storage element to said first battery cell.

36. The balancing circuit of claim 35, wherein a third battery cell has a third voltage level, said third voltage level higher than said first voltage level, and wherein said charge shuttling circuit is configured to shuttle charges from said third battery cell and said second battery cell to said first battery cell.

37. The balancing circuit of claim 22, wherein said balance signal is provided when said power sources are in a discharge mode.

38. An electronic device capable of being powered by a battery pack having a plurality of battery cells, said electronic device comprising:

a monitoring circuit for accurately monitoring a voltage level from each of said plurality of battery cells, said monitoring circuit comprising;

an analog to digital converter (ADC) configured to accept an analog voltage signal from each of said plurality of battery cells and convert each said analog voltage signal to a digital signal representative of a voltage level of each said battery cell; and

a processor configured to receive each said digital signal and to provide a safety alert signal based on at least one of said digital signals.

39. The electronic device of claim 38, wherein said safety alert signal is a charging alert signal if at least one of said digital signals is representative of a voltage level of one of said battery cells greater than an over voltage threshold value during a predetermined monitoring time interval while said plurality of battery cells are being charged.

40. The electronic device of claim 39, wherein said charging alert signal is provided if one of said digital signals is representative of a voltage level of one of said battery cells greater than said over voltage threshold value while said plurality of battery cells are being charged.

41. The electronic device of claim 39, wherein said over voltage threshold level is adjustable by said processor.

42. The electronic device of claim 41, wherein said over voltage threshold level is adjustable by said processor based on ambient temperature.

43. The electronic device of claim 38, wherein said safety alert signal is a discharge alert signal if at least one of said digital signals is representative of a voltage level of one of said battery cells less than an under voltage threshold value during a predetermined monitoring time interval while said plurality of battery cells are being discharged.

44. The electronic device of claim 43, wherein said discharge alert control signal is provided if one of said digital signals is representative of a voltage level of one of said battery cells less than said under voltage threshold value while said plurality of battery cells are being discharged.

45. The electronic device of claim 43, wherein said under voltage threshold level is adjustable by said processor.

46. The electronic device of claim 45, wherein said over under voltage threshold level is adjustable by said processor based on ambient temperature.

47. The electronic device of claim 38, wherein said ADC is an averaging type ADC.

48. The electronic device of claim 47, wherein said averaging type ADC samples a voltage level for each said battery cell a plurality of times over a sampling period before converting said analog voltage signal to an associated digital signal.

49. The electronic device of claim 38, wherein said ADC has a resolution, and said resolution is adjustable by said processor.

50. The electronic device of claim 38, wherein said monitoring circuit further comprises a switch network coupled between said plurality of battery cells and said ADC said switch network having a plurality of switches controlled by said processor, said switch network enabling each of said plurality of battery cells to be directly coupled to said ADC through said switch network.

51. The electronic device of claim 38, wherein said ADC has a positive input terminal and a negative input terminal, wherein a first offset value for a first battery cell being is determined by coupling one terminal of said first battery cell to both said positive and said negative input terminal of said ADC, wherein said processor is further configured to apply said first offset value to a first digital signal representative of a voltage level of said first battery cell thereby providing a first calibrated digital signal.

52. The electronic device of claim 51, wherein a second offset value for a second battery cell is determined by coupling one terminal of said second battery cell to both said positive and said negative input terminal of said ADC, wherein said processor is further configured to apply said second offset value to a second digital signal representative of a voltage level of said second battery cell thereby providing a second calibrated digital signal.

53. The electronic device of claim 38, wherein said ADC samples a voltage level of each said battery cell once every sampling time period, wherein said sampling time period is adjustable by said processor.

54. The electronic device of claim 53, wherein said sampling time period has a first time interval during a first condition, and said sampling time period has a second time interval during a second condition, said second time interval being longer than said first time interval and said second condition being a sleep mode of said plurality of battery cells.

55. The electronic device of claim 43, wherein said safety alert signal is a first discharge alert signal if at least one of said digital signals is representative of a voltage level of one of said battery cells less than a first under voltage threshold level during said predetermined monitoring time interval while said plurality of battery cells are being discharged, wherein said first under voltage threshold level is greater than said under voltage threshold level.

56. The electronic device of claim 55, wherein said safety alert signal is a second discharge alert signal if at least one of said digital signals is representative of a voltage level of one of said power sources less than a second under voltage level during said predetermined monitoring time interval while said plurality of power sources are being discharged, wherein said second under voltage threshold level is less than first under voltage threshold level and greater than said under voltage threshold level.

57. The electronic device of claim 38, wherein said monitoring circuit further comprises:

a protection circuit configured to compare a signal representative of a current level associated with said battery pack to an over current threshold and to provide an over current alert signal to said processor if said current level is greater than said over current threshold.

58. The electronic device of claim 57, wherein said protection circuit is further configured to compare said signal representative of said current level associated with said battery pack to a short circuit current threshold and to provide a short circuit current alert signal to said processor if said current level is greater than said short circuit current threshold.

59. The electronic device of claim 38, said electronic device further comprising:

a battery gauge configured to provide a battery gauge output signal representative of the remaining useful life of said battery pack, said battery gauge configured to receive each of said digital signals representative of said voltage level of each said battery and provide said battery gauge output signal based on said digital signals.

60. An electronic device capable of being powered by a battery pack having a plurality of battery cells, said electronic device comprising:

a balancing circuit, said balancing circuit comprising;

an analog to digital converter (ADC) configured to accept an analog voltage signal from each of said plurality of battery cells and convert each said analog voltage signal to a digital signal representative of a voltage level of each said battery cell; and

a processor configured to receive each said digital signal and to provide a balance signal if at least two of said digital signals are representative of a voltage difference between a first voltage level of a first battery cell and a second voltage level of a second battery cell greater than a battery cell balance threshold.

61. The electronic device of claim 60, wherein said electronic device further comprises:

a bleeding network circuit configured to accept said balance signal and provide a bleeding current to any one of said plurality of battery cells in response to said balance signal.

62. The electronic device of claim 61, wherein said bleeding network circuit provides a first bleeding current to said second battery cell if said second voltage level of said second battery cell is greater than said first voltage level of said first battery cell, said bleeding network circuit applying said first bleeding current for a first time interval to reduce said second voltage level to a level substantially equal to said first voltage level.

63. The electronic devices of claim 62, wherein a third battery cell has a third voltage level, said third voltage level greater than said first voltage level, said third voltage level greater than said second voltage level, said bleeding network circuit applying said first bleeding current to said third battery cell for a second time interval to reduce said third voltage level to said level substantially equal to said first voltage level, wherein at least some portion of said first time interval and said second time interval overlap.

64. The electronic device of claim 63, wherein said first time interval has a first starting time and said second time interval has a second starting time, said first starting time substantially equal to said second starting time and wherein said second time interval is longer than said first time interval.

65. The electronic device of claim 61, wherein said bleeding current provided by said bleeding network circuit is adjustable in response to said balance signal from said processor.

66. The electronic device of claim 65, wherein a third battery cell has a third voltage level, and wherein said second voltage level is greater than said first voltage level by a first difference level, and said third voltage level is greater than said first voltage level by a second difference level, and wherein said second difference level is greater than said first difference level, and wherein said bleeding network circuit provides a first bleeding current to said second battery cell and a second bleeding current to said third battery cell, said second bleeding current greater than said first bleeding current.

67. The electronic device of claim 65, wherein said bleeding network circuit comprises a plurality of bleeding circuits associated with each said plurality of battery cells, at least one of said plurality of bleeding circuits comprising:

a first switch having a first resistive element coupled to a terminal of said first switch, said first resistive element having a first resistive value; and

a second switch having a second resistive element coupled to a terminal of said second switch, said second resistive element having a second resistive value, said second resistive value less than said first resistive value.

68. The electronic device of claim 67, wherein a first bleeding current is applied to an associated battery cell if said first switch is ON and said second switch is OFF, and a second bleeding current is applied to said associated battery cell if said first switch if OFF and said second switch if ON, wherein said second bleeding current is greater than said first bleeding current.

69. The electronic device of claim 60, wherein said electronic device further comprises:

a charge shuttling circuit configured to shuttle charges among said plurality of battery cells in response to said balance signal.

70. The electronic device of claim 69, wherein said charge shuttling circuit is configured to shuttle charges from said second battery cell to said first battery cell if said second voltage level is greater than said first voltage level.

71. The electronic device of claim 69, wherein said charge shuttling circuit comprises an energy storage element.

72. The electronic device of claim 71, wherein said energy storage element comprises a capacitor.

73. The electronic device of claim 71, wherein said balancing circuit further comprises:

a switch network coupled between said plurality of battery cells and said ADC, said processor controlling said switch network to couple said second battery cell to said energy storage element to transfer a charge from said second battery cell to said energy storage element, said processor controlling said switch network to couple said first battery cell to said energy storage element to transfer said charge from said energy storage element to said first battery cell.

74. The electronic device of claim 72, wherein a third battery cell has a third voltage level, said third voltage level higher than said first voltage level, and wherein said charge shuttling circuit is configured to shuttle charges from said third battery cell and said second battery cell to said first battery cell.

75. The electronic device of claim 60, wherein said balance signal is provided when said battery cells are in a discharge mode.

76. A balancing circuit comprising:

an analog to digital converter (ADC) configured to accept an analog voltage signal from each of a plurality of battery cells of a battery pack and convert each said analog voltage signal to a digital signal representative of a voltage level of each said battery cell; and

a processor configured to receive each said digital signal and to provide a pre-balance signal during a second mode before a voltage difference between a first voltage level of a first battery cell and a second voltage level of a second battery cell exceeds a battery cell balance threshold if said voltage difference existed during a first mode.

77. The balancing circuit of claim 76, wherein said first mode is a first discharging mode of said battery pack and said second mode is a second discharging mode of said battery pack.

78. The balancing circuit of claim 76, wherein said first mode is a first charging mode of said battery pack and said second mode is a second charging mode of said battery pack.

79. The balancing circuit of claim 76, wherein said pre-balance signal is provided to a charge shuttling circuit configured to shuttle charges among said plurality of battery cells in response to said pre-balance signal.

80. The balancing circuit of claim 79, wherein said charge shuttling circuit is configured to shuttle charges from said second battery cell to said first battery cell if said second voltage level was greater than said first voltage level during said first mode.

81. The balancing circuit of claim 79, wherein said charge shuttling circuit comprises an energy storage element.

82. A method of balancing voltage levels for a plurality of battery cells of a battery pack, said method comprising the steps of:

converting a first analog voltage signal from a first cell to a first digital signal representative of said first analog voltage signal;

converting a second analog voltage signal from a second cell to a second digital signal representative of said second analog voltage signal;

determining a difference between said first voltage level and said second voltage level;

comparing said difference to a battery cell balance threshold; and

providing a balance signal if said difference is greater than said battery cell balance threshold.

83. A method of pre-balancing voltage levels for a plurality of battery cells of a battery pack, said method comprising the steps of:

converting a first analog voltage signal from a first cell to a first digital signal representative of said first analog voltage signal;

converting a second analog voltage signal from a second cell to a second digital signal representative of said second analog voltage signal;

determining a difference between said first voltage level and said second voltage level during a first time period;

comparing said difference to a battery cell balance threshold; and

providing a pre-balance signal during a second time period before said difference between said first voltage level and said second voltage level exceeds said battery cell balance threshold if said difference exceeded said battery cell balance threshold during a first time period.

84. The method of claim 83, wherein said first time period is a first discharging mode of said battery pack and said second time period is a second discharging mode of said battery pack.

85. The method of claim 83, wherein said first time period is a first charging mode of said battery pack and said second time period is a second charging mode of said battery pack.