Equalization and decision-directed loops with trellis demodulation in high definition TV

• US 20040258184A1
• Filed: 07/21/2004
• Published: 12/23/2004
• Est. Priority Date: 11/03/1998
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Tan, Loke Kun, Jaffe, Steven T., Liu, Tian-Min
• Granted Patent: US 7,474,695 B2
• Time in Patent Office: Days
• US Class Current: 375/350
• CPC Class Codes: H04B 1/68 for wholly or partially suppressing the carrier or one side band
• CPC Class Codes: H04L 2025/03382 Single of vestigal sideband
• CPC Class Codes: H04L 2025/0342 QAM
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2027/0032 at baseband and passband
• CPC Class Codes: H04L 2027/0042 the equaliser providing the offset correction per se
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0087 Out-of-band signals, (e.g. pilots)
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/066 Carrier recovery circuits H04L27/2271 takes precedence
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 27/3427 in which the constellation is the n - fold Cartesian product of a single underlying two-dimensional constellation
• CPC Class Codes: H04L 27/3827 in which the carrier is recovered using only the demodulated baseband signals
• CPC Class Codes: H04N 11/24 High-definition television systems
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
• CPC Class Codes: H04N 5/211 Ghost signal cancellation H04N23/81 takes precedence
• CPC Class Codes: H04N 5/44 : Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27

Abstract

Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE'"'"'s ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

Claims

1. A method for processing a digital input signal with a receiver having a feed forward equalizer (FFE) with adjustable taps and a decision feedback equalizer (DFE), the method comprising:

applying an input signal to the FFE to produce a first frequency compensated signal;

producing a second frequency compensated signal from the DFE;

combining the first and second signals to produce a third frequency compensated signal;

producing tentative decisions of the third signal based on the history of prior decisions;

applying the tentative decisions to the DFE;

producing an error signal representative of the difference between the tentative decisions and the third signal; and

adjusting the taps of the ffe responsive to the error signal so as to reduce the error signal;

2. The method of claim 1, in which the input signal is trellis encoded and producing tentative decisions decodes the input signal.

3. The method of claim 2, in which the DFE has adjustable taps, the method additionally comprising adjusting the taps of the DFE responsive to the error signal so as to reduce the error signal.

4. The method of claim 3, in which the receiver has a timing loop that recovers data embedded in the digital signal, the method additionally comprising adjusting the timing loop responsive to the error signal to improve the recovery of the embedded data.

5. The method of claim 4, in which the receiver has a carrier loop that derotates the input signal responsive to the error signal, the method additionally comprising adjusting the carrier loop responsive to the error signal to derotate the input signal.

6. The method of claim 1, in which the DFE has adjustable taps, the method additionally comprising adjusting the taps of the DFE responsive to the error signal so as to reduce the error signal.

7. The method of claim 1, in which the receiver has a timing loop that recovers data embedded in the digital signal, the method additionally comprising adjusting the timing loop responsive to the error signal to improve the recovery of the embedded data.

8. The method of claim 1, in which the receiver has a carrier loop that derotates the input signal responsive to the error signal, the method additionally comprising adjusting the carrier loop responsive to the error signal to derotate the input signal.

9. The method of claim 1, in which the input signal is delayed so it has the same time stamp as the tentative decisions and is trellis encoded, and producing tentative decisions decodes the input signal.

10. The method of claim 1, in which the DFE has adjustable taps, the method additionally comprising delaying the input signal so it has the same time stamp as the tentative decisions and adjusting the taps of the DFE responsive to the error signal so as to reduce the error signal.

11. The method of claim 1, in which the receiver has a timing loop that recovers data embedded in the digital signal, the method additionally comprising delaying the input signal so it has the same time stamp as the tentative decisions and adjusting the timing loop responsive to the error signal to improve the recovery of the embedded data.

12. The method of claim 1, in which the receiver has a carrier loop that derotates the input signal responsive to the error signal, the method additionally comprising delaying the input signal so it has the same time stamp as the tentative decisions and adjusting the carrier loop responsive to the error signal to derotate the input signal.