Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same

• US 20040262768A1
• Filed: 05/13/2004
• Published: 12/30/2004
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Hyuck-Jin, Byun, Gwang-Seon, Shin, Heui-Won, Kim, Sun-Joon, Cho, Tai-Heui
• Granted Patent: US 7,180,154 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 23/5258 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.

Claims

1. An integrated circuit device comprising:

an integrated circuit substrate;

first through fourth spaced apart lower interconnects on the integrated circuit substrate, the third and fourth spaced apart lower interconnects being parallel to the first and second lower interconnects;

a first fuse on the first and second lower interconnects, the first fuse being between the first and second lower interconnects and electrically coupled to the first and second lower interconnects; and

a second fuse, spaced apart from the first fuse, on the third and fourth lower interconnects, the second fuse being between the third and fourth lower interconnects and electrically coupled to the third and fourth lower interconnects.

2. The integrated circuit device of claim 1, further comprising first, second and third intermediate interconnects on the integrated circuit substrate having surfaces that are substantially planar with surfaces of the first and second fuses, wherein the first intermediate, interconnect is on the first lower interconnect and electrically coupled to the first lower interconnect, wherein the second intermediate interconnect is on the second and fourth lower interconnects and is electrically coupled to the second and fourth lower interconnects and wherein the third intermediate interconnect is on the third lower interconnect and is electrically coupled to the third lower interconnect.

3. The integrated circuit device of claim 2, further comprising first, second and third lower metal interconnects on the first, second and third intermediate interconnects, respectively, and electrically coupled to the first, second and third intermediate interconnects, respectively.

4. The integrated circuit device of claim 2, further comprising a fuse guard ring on the integrated circuit substrate that surrounds the first and second fuses.

5. The integrated circuit device of claim 4, wherein the fuse guard ring comprises:

an intermediate interconnect guard ring between the first and second fuses and the first, second and third intermediate interconnects;

a first metal guard ring plug on the intermediate interconnect guard ring;

a first metal guard ring on the first metal guard ring plug;

a second metal guard ring plug on the first metal guard ring; and

a second metal guard ring on the second metal guard ring plug.

6. The integrated circuit device of claim 2, further comprising first, second, third and fourth fuse contact plugs, wherein the first fuse is electrically coupled to the first and second lower interconnects through the first and second fuse contact plugs and wherein the second fuse is electrically coupled to the third and fourth lower interconnects through the third and fourth fuse contact plugs.

7. The integrated circuit device of claim 6 wherein the first, second, third and fourth fuse contact plugs comprise a barrier metal layer and a metal plug layer on the barrier metal layer.

8. The integrated circuit device of claim 7 wherein the barrier metal layer comprises a

titanium nitride layer.

9. The integrated circuit device of claim 1 wherein the first, second, third and fourth lower interconnects comprise non-corrosive material layers.

10. The integrated circuit device of claim 9 wherein the non-corrosive material layers comprise at least one of a polysilicon layer and a polycide layer.

11. The integrated circuit device of claim 2 wherein the first, second and third intermediate interconnects and the first and second fuses comprise tungsten layers.

12. A fuse region of an integrated circuit device comprising:

an integrated circuit substrate;

a plurality of spaced apart fuses on the integrated circuit substrate; and

a fuse guard ring on the integrated circuit substrate that surrounds the plurality of fuses.

13. The fuse region of claim 12 wherein the fuse guard ring comprises:

an intermediate interconnect guard ring having a surface that is substantially planar to surfaces of the plurality of fuse regions;

a first metal guard ring plug on the intermediate interconnect guard ring;

a first metal guard ring on the first metal guard ring plug;

a second metal guard ring plug on the first metal guard ring; and

a second metal guard ring on the second metal guard ring plug.

14. An integrated circuit device comprising:

an integrated circuit substrate including first and second regions;

a lower interlayer insulating layer on the integrated circuit substrate;

a plurality of parallel lower interconnects on the integrated circuit substrate, odd-numbered ones of the plurality lower interconnects being in the first region of the integrated circuit substrate and even-numbered ones of the plurality of lower interconnects being in the second region of the integrated circuit substrate;

a plurality of parallel fuses on the plurality of lower interconnects, even-numbered ones of the plurality of fuses being in the first region of the integrated circuit substrate and electrically coupled to respective even-numbered ones of the plurality of lower interconnects and odd-numbered ones of the plurality of fuses being in the second region of the integrated circuit substrate and electrically coupled to respective odd-numbered ones of the plurality of lower interconnects;

a plurality of upper interconnects on the plurality of parallel fuses, a first group of the plurality of upper interconnects being electrically coupled the odd-numbered ones of the plurality of lower interconnects and the even-numbered ones of the plurality of fuses and a second group of the plurality of upper interconnects being electrically coupled to the even-numbered ones of the plurality of lower interconnects and to the odd-numbered ones of the plurality of fuses.

15. The integrated circuit device of claim 14 further comprising:

an intermediate insulating layer on the plurality of lower interconnects;

an upper insulating layer on the plurality of fuses;

a plurality of odd-numbered intermediate interconnects on the odd numbered ones of the plurality of lower interconnects that are adjacent to the first region of the integrated circuit substrate, the plurality of odd-numbered intermediate interconnects being interposed between the intermediate interlayer insulating layer and the upper interlayer insulating layer; and

a plurality of even-numbered intermediate interconnects on the even numbered ones of the plurality of lower interconnects that are adjacent to the second region, the plurality of even-numbered intermediate interconnects being interposed between the intermediate interlayer insulating layer and the upper interlayer insulating layer, wherein the odd-numbered ones of the plurality of upper interconnects are electrically coupled to the plurality of odd-numbered lower interconnects through the plurality of odd-numbered intermediate interconnects and wherein the even-numbered ones of the plurality of upper interconnects are electrically coupled to the plurality of even-numbered lower interconnects through the plurality of even-numbered intermediate interconnects.

16. The integrated circuit device of claim 15 wherein the plurality of odd-numbered intermediate interconnects, the plurality of even-numbered intermediate interconnects and the plurality of fuses comprise the same material layer.

17. The integrated circuit device of claim 16 wherein the first group of upper interconnects are adjacent to the first region of the integrated circuit substrate and opposite the second region of the integrated circuit substrate and wherein the second group of upper interconnects are adjacent to the second region of the integrated circuit substrate and opposite the first region of the integrated circuit substrate.

18. The integrated circuit device of claim 15 wherein the even-numbered ones of the plurality of fuses are on extension lines of the even-numbered ones of the plurality of lower interconnects and the odd-numbered ones of the plurality of fuses are on extension lines of the odd-numbered ones of the plurality of lower interconnects.

19. The integrated circuit device of claim 15 wherein the plurality of lower interconnects comprise non-corrosive material layers.

20. The integrated circuit device of claim 19 wherein the non-corrosive material layer comprises at least one of a polysilicon layer and a tungsten polycide layer.

21. The integrated circuit device of claim 15 wherein the plurality of fuses comprise tungsten layers.

22. An integrated circuit device comprising:

an integrated circuit substrate having first and second regions;

a plurality of parallel lower interconnects, odd-numbered ones of the plurality of lower interconnects being in the first region of the integrated circuit substrate and even-numbered ones of the plurality of lower interconnects being in the second region of the integrated circuit substrate;

a plurality of fuses on the first and second regions of the integrated circuit substrate, the plurality of fuses having overlap portions with the plurality of lower interconnects; and

a plurality of upper interconnects, a first group of the plurality of upper interconnects being electrically coupled to ends of ones of the plurality of fuses adjacent to the first region of the integrated circuit substrate, a second group of the plurality of upper interconnects being electrically coupled to ends of ones of the plurality of fuses adjacent to the second region of the integrated circuit substrate, ends of the overlap portions of the plurality of fuses being electrically coupled to ends of the plurality of lower interconnects thereunder.

23. The integrated circuit device of claim 22 wherein the plurality of lower interconnects comprise non-corrosive material layers.

24. The integrated circuit device of claim 23 wherein the non-corrosive material layer comprises at least one of a polysilicon layer and a polycide layer.

25. The integrated circuit device of claim 22 wherein the plurality of fuses comprise tungsten layers.

26. A method of forming an integrated circuit device comprising:

forming first through fourth spaced apart lower interconnects on an integrated circuit substrate, the third and fourth spaced apart lower interconnects being parallel to the first and second lower interconnects;

forming a first fuse on the first and second lower interconnects, the first fuse being between the first and second lower interconnects and electrically coupled to the first and second lower interconnects; and

forming a second fuse, spaced apart from the first fuse, on the third and fourth lower interconnects, the second fuse being between the third and fourth lower interconnects and electrically coupled to the third and fourth lower interconnects.

27. The method of claim 26, further comprising forming first, second and third intermediate interconnects on the integrated circuit substrate having surfaces that are substantially planar with surfaces of the first and second fuses, wherein the first intermediate interconnect is on the first lower interconnect and electrically coupled to the first lower interconnect, wherein the second intermediate interconnect is on the second and fourth lower interconnects and is electrically coupled to the second and fourth lower interconnects and wherein the third intermediate interconnect is on the third lower interconnect and is electrically coupled to the third lower interconnect.

28. The method of claim 27, further comprising forming first, second and third lower metal interconnects on the first, second and third intermediate interconnects, respectively, and electrically coupled to the first, second and third intermediate interconnects, respectively.

29. The method of claim 27, further comprising forming a fuse guard ring on the integrated circuit substrate that surrounds the first and second fuses.

30. The method of claim 29, wherein forming the fuse guard ring comprises:

forming an intermediate interconnect guard ring between the first and second fuses and the first, second and third intermediate interconnects;

forming a first metal guard ring plug on the intermediate interconnect guard ring;

forming a first metal guard ring on the first metal guard ring plug;

forming a second metal guard ring plug on the first metal guard ring; and

forming a second metal guard ring on the second metal guard ring plug.

31. The method of claim 27, further comprising forming first, second, third and fourth fuse contact plugs, wherein the first fuse is electrically coupled to the first and second lower interconnects through the first and second fuse contact plugs and wherein the second fuse is electrically coupled to the third and fourth lower interconnects through the third and fourth fuse contact plugs.

32. The method of claim 31 wherein the forming the first, second, third and fourth fuse contact plugs comprise forming a barrier metal layer and forming a metal plug layer on the barrier metal layer.

33. A method of forming a fuse region comprising:

forming a plurality of spaced apart fuses on an integrated circuit substrate; and

forming a fuse guard ring on the integrated circuit substrate that surrounds the plurality of fuses.

34. The method of claim 33 wherein forming the fuse guard ring comprises:

forming an intermediate interconnect guard ring having a surface that is substantially planar to surfaces of the plurality of fuse regions;

forming a first metal guard ring plug on the intermediate interconnect guard ring;

forming a first metal guard ring on the first metal guard ring plug;

forming a second metal guard ring plug on the first metal guard ring; and

forming a second metal guard ring on the second metal guard ring plug.

35. A method of forming an integrated circuit comprising:

forming a lower interlayer insulating layer on an integrated circuit substrate including first and second regions;

forming a plurality of parallel lower interconnects on the integrated circuit substrate, odd-numbered ones of the plurality lower interconnects being in the first region of the integrated circuit substrate and even-numbered ones of the plurality of lower interconnects being in the second region of the integrated circuit substrate;

forming a plurality of parallel fuses on the plurality of lower interconnects, even-numbered ones of the plurality of fuses being in the first region of the integrated circuit substrate and electrically coupled to respective even-numbered ones of the plurality of lower interconnects and odd-numbered ones of the plurality of fuses being in the second region of the integrated circuit substrate and electrically coupled to respective odd-numbered ones of the plurality of the lower interconnects; and

forming a plurality of upper interconnects on the plurality of parallel fuses, a first group of the plurality of upper interconnects being electrically coupled the odd-numbered ones of the lower interconnects and the even-numbered ones of the plurality of fuses and a second group of the plurality of upper interconnects being electrically coupled to the even-numbered ones of the plurality of lower interconnects and to the odd-numbered ones of the plurality of fuses.

36. The method of claim 35 further comprising:

forming an intermediate insulating layer on the plurality of lower interconnects;

forming an upper insulating layer on the plurality of fuses;

forming a plurality of odd-numbered intermediate interconnects on the odd-numbered ones of the plurality of lower interconnects that are adjacent to the first region of the integrated circuit substrate, the plurality of odd-numbered intermediate interconnects being interposed between the intermediate interlayer insulating layer and the upper interlayer insulating layer; and

forming a plurality of even-numbered intermediate interconnects on the even numbered ones of the plurality of lower interconnects that are adjacent to the second region, the even-numbered intermediate interconnects being interposed between the intermediate interlayer insulating layer and the upper interlayer insulating layer, wherein the odd-numbered ones of the plurality of upper interconnects are electrically coupled to the plurality of odd-numbered lower interconnects through the plurality of odd-numbered intermediate interconnects and wherein the even-numbered ones of the plurality of upper interconnects are electrically coupled to the plurality of even-numbered lower interconnects through the plurality of even-numbered intermediate interconnects.

37. A method of forming integrated circuit devices comprising:

forming a plurality of parallel lower interconnects, odd-numbered ones of the plurality of lower interconnects being in the first region of an integrated circuit substrate and even-numbered ones of the plurality of lower interconnects being in a second region of the integrated circuit substrate;

forming a plurality of fuses on the first and second regions of the integrated circuit substrate, the plurality of fuses having overlap portions with the plurality of lower interconnects; and

forming a plurality of upper interconnects, a first group of the plurality of upper interconnects being electrically coupled to ends of ones of the plurality of fuses adjacent to the first region of the integrated circuit substrate, a second group of the plurality of upper interconnects being electrically coupled to ends of ones of the plurality of fuses adjacent to the second region, ends of the overlap portions of the plurality of fuses being electrically coupled to ends of the plurality of lower interconnects thereunder.