Digitally-synthesized loop filter method and circuit particularly useful for a phase locked loop

• US 20040263225A1
• Filed: 07/20/2004
• Published: 12/30/2004
• Est. Priority Date: 07/10/2000
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Michael H. Perrott, Rex T. Baird, Yunteng Huang
• Inventors: Huang, Yunteng, Perrott, Michael H., Baird, Rex T.
• Granted Patent: US 7,613,267 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In some embodiments, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block.

Claims

1. A method for controlling an oscillator in a phase locked loop system, said method comprising:

generating a digital representation of a phase error signal of the phase locked loop system;

generating a multi-bit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and

generating an oscillator control signal corresponding to the accumulated digital phase error signal.

2. The method defined by claim 1 wherein the digital phase error signal comprises a quantized-time and quantized-value signal which encodes polarity of phase error.

3. The method defined by claim 1 wherein the digital phase error signal comprises a quantized-time and quantized-value signal which linearly encodes phase error.

4. The method defined by claim 1 wherein the generating the digital representation of the phase error signal comprises:

generating an analog representation of a phase error signal; and

converting the analog phase error signal into a corresponding digital phase error signal.

5. The method defined by claim 4 wherein the converting step comprises delta-sigma encoding the digital phase error signal.

6. The method defined by claim 1 wherein the generating a multi-bit accumulated digital phase error signal comprises:

accumulating successive values of a digital input signal representing the phase error, and providing a multi-bit accumulated digital phase error signal.

7. The method defined by claim 6 wherein:

the oscillator control signal corresponds to a configurable number of bits of the multi-bit accumulated digital phase error signal .

8. The method defined by claim 6 wherein the accumulating successive values of a digital input signal representing the phase error step comprises:

clocking a lower-order accumulator circuit at a first clock rate, said lower-order accumulator circuit having an input responsive to the digital input signal representing the phase error, and having at least one output; and

clocking an upper-order accumulator circuit at a second clock rate, said upper-order accumulator circuit having an input coupled to an output of the lower-order accumulator circuit, and having an output for conveying a portion of the multi-bit accumulated digital phase error signal;

wherein the respective outputs of the lower-order accumulator circuit and the upper-order accumulator circuit together comprise the multi-bit accumulated digital phase error signal.

9. The method defined by claim 8 wherein:

the second clock rate is lower than the first clock rate.

10. The method defined by claim 8 further comprising:

generating the oscillator control signal corresponding to only a portion of the upper-order and lower-order accumulator bits forming the accumulated digital phase error signal.

11. The method defined by claim 10 wherein:

generating the oscillator control signal corresponding to only upper-order accumulator bits forming the accumulated digital phase error signal.

12. The method defined by claim 6 further comprising:

decimating the digital phase error signal and accumulating successive values of the decimated digital phase error signal to generate the multi-bit accumulated digital phase error signal.

13. The method defined by claim 1 wherein:

the oscillator control signal comprises an analog representation of at least a most-significant-bit portion of the accumulated digital phase error signal.

14. The method defined by claim 1 wherein:

the multi-bit accumulated digital phase error signal is computed to a greater number of bits than that to which the oscillator control signal corresponds.

15. The method defined by claim 1 further comprising:

providing the oscillator control signal as an analog signal.

16. The method defined by claim 15 further comprising:

low-pass filtering the analog oscillator control signal.

17. The method defined by claim 1 further comprising:

configuring a number of bits in the accumulated digital phase error signal to determine an effective value of capacitance within a filter portion of the phase locked loop system.

18. The method defined by claim 17 further comprising:

varying the number of bits in the accumulated digital phase error signal to alter an operating characteristic of the phase locked loop system.

19. The method defined by claim 1 implemented entirely within an integrated circuit.

20. The method defined by claim 1 implemented entirely within an integrated circuit which is configured to recover clock and data from an incoming data signal having more than one possible data rate, said method further comprising varying the number of bits in the accumulated digital phase error signal based upon the data rate of the incoming data input signal.

21. The method defined by claim 20 wherein the incoming data input signal is a SONET signal.