Digital signal processing apparatus and digital signal processing method

• US 20040268203A1
• Filed: 07/21/2004
• Published: 12/30/2004
• Est. Priority Date: 09/01/1999
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Koyata, Tomohiro
• Granted Patent: US 7,197,093 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G10L 19/0208 Subband vocoders
• CPC Class Codes: G10L 21/0364 for improving intelligibility

Abstract

A digital signal of which input data has been segmented as block each having a predetermined data amount and highly efficiently encoded along with an adjacent block is decoded, edited, and then highly efficiently encoded. A delay that takes place in such signal processes is compensated. Thus, part of a digital signal that has been highly efficiently encoded digital signal can be edited.

Claims

1. :

A digital signal processing apparatus for processing an input digital signal that has been segmented as blocks each having a predetermined data amount and highly efficiently encoded along with adjacent blocks, comprising;

decoding means for decoding the highly efficiently encoded digital signal along with adjacent blocks;

modifying process means for modifying the decoded digital signal;

encoding means for highly efficiently encoding the modified digital signal along with adjacent blocks; and

delay compensating means for compensating a delay of the decoded signal decoded by said decoding means.

3. :

The digital signal processing apparatus as set forth in claim 1,

wherein said decoding means decodes the digital signal corresponding to the information compressed parameter for each block.

4. :

The digital signal processing apparatus as set forth in claim 1, further comprising;

operating means for allowing the user to designate a highly efficiently encoded digital signal to be edited.

5. :

The digital signal processing apparatus as set forth in claim 1,

wherein the input signal that has been highly efficiently encoded is read from a record medium.

6. :

The digital signal processing apparatus as set forth in claim 5,

wherein a delay of the digital signal that has been highly efficiently encoded by said encoding means is compensated by said delay compensating means and then the compensated signal is written to the record medium so that the phase of the compensated signal matches the phase of the digital signal that has been read from the record medium.

2. :

(Canceled).

7. :

A digital signal processing method for processing an input digital signal that has been segmented as blocks each having a predetermined data amount and highly efficiently encoded along with adjacent blocks, comprising the steps of;

(a) decoding the highly efficiently encoded digital signal along with adjacent blocks;

(b) modifying the decoded digital signal; and

(c) highly efficiently encoding the changed digital signal along with adjacent blocks and compensating a delay of the decoded signal decoded at step (a).

9. :

The digital signal processing method as set forth in claim 7,

wherein step (a) is performed by decoding the digital signal corresponding to the information compressed parameter for each block.

10. :

The digital signal processing method as set forth in claim 7, further comprising the step of;

(j) allowing the user to designate a highly efficiently encoded digital signal to be edited.

11. :

The digital signal processing method as set forth in claim 7,

wherein the input signal that has been highly efficiently encoded is read from a record medium.

12. :

The digital signal processing method as set forth in claim 11,

wherein a delay of the digital signal that has been highly efficiently encoded at step (a) is compensated at step (c) and then the compensated signal is written to the record medium so that the phase of the compensated signal matches the phase of the digital signal that has been read from the record medium.

8. :

(Canceled).