Pulse signal generator and display device

• US 20050017778A1
• Filed: 06/07/2004
• Published: 01/27/2005
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tateishi, Tetsuo, Nakamura, Hiroko, Nogawa, Masashi
• Granted Patent: US 7,009,440 B2
• Time in Patent Office: Days
• US Class Current: 327/165
• CPC Class Codes: G09G 2300/06 Passive matrix structure, i.e. with direct application of both column and row voltages to the light emitting or modulating elements, other than LCD or OLED
• CPC Class Codes: G09G 2310/0221 with use of split matrices G09G3/3644 and G09G3/3666 take precedence
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/2088 with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3216 using a passive matrix
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

The objective of this invention is to provide a pulse signal generator with a simple constitution that can reduce the number of signals required for setting the pulse width, as well as a display device using said pulse signal generator. Pulse assignment signal DP0 input to the initial stage of pulse signal generating units PG(i,0)-PG(i,39) connected in cascade is sequentially transferred towards the last stage of the cascade connection. After transfer of the pulse assignment signal to the pulse signal generating unit in each stage, the count value of said pulse signal generating unit is initialized. Then, the pulses of pulse strings PS0-PS39 in the various pulse signal generating units are counted. The count value of the pulse string is compared to the pulse assignment signal in the comparison unit of each pulse signal generating unit, and, in accordance with the comparison result, the level of the drive pulse signal of the LED is inverted. The pulse intervals (pulse timing) of pulse strings PS0-PS39 are controlled individually by control unit 1 so that the drive pulse signal output from the pulse signal generating unit has the desired pulse width.

Claims

1. A pulse signal generator comprising:

the pulse signal generator generates plural pulse signals and comprises;

a pulse arrival notification means that reports the arrival of the pulse, which is contained in the input pulse string and which is input when an enable signal indicating permission for pulse input is given, together with the information that specifies said pulse;

a pulse arrival judgment means, which uses the pulse assignment signals corresponding to said pulse signals to be generated as input, and which determines whether the pulse assigned with said pulse assignment signal has arrived for each of said pulse signals on the basis of the notification of said pulse arrival notification means;

and a pulse signal output means that inverts the output level of the pulse signal, for which arrival of said assigned pulse is judged by said pulse arrival judgment means, synchronization with the arrival of said pulse.

2. The pulse signal generator described in claim 1, comprising:

a first signal holding means that holds the signal input to the first input terminal and outputs the held signal to a first output terminal synchronously with the input clock signal;

wherein said pulse arrival notification means has the signal held in said first signal holding means input to it as said enable signal.

3. The pulse signal generator described in claim 1 further comprising:

a second signal holding means that holds the signal input to a second input terminal and outputs the held signal to a second output terminal synchronously with said clock signal; and

a third signal holding means that holds the signal held in said second signal holding means synchronously with an input latch signal;

wherein said pulse arrival judgment means has the signal held in said third signal holding means input to it as said pulse assignment signal.

4. The pulse signal generator described in claim 3, wherein said clock signal contains clock pulses, one at a prescribed period, with the result of a prescribed logic operation made between said clock pulses and said pulse string becoming a prescribed value;

and comprising a logic operation means that outputs said result of the logic operation between said clock signal and said pulse string as said latch signal.

5. The pulse signal generator described in claim 4, wherein said pulse arrival notification means counts the pulses that are contained in said pulse string and that are input when said enable signal indicating permission for pulse input is given, and initializes said counting result corresponding to the result of operation of said logic operation means;

and wherein said pulse arrival judgment means compares said pulse assignment signal to the counting result of said pulse arrival notification means, and judges the arrival of said assigned pulse corresponding to the result of the comparison.

6. The pulse signal generator described in claim 1, further comprising a packet signal processing means, which determines whether the packet signal is to be received corresponding to the identification information contained in the input packet signal, and, when decision is made to receive, extracts said enable signal and/or said pulse assignment signal from said packet signal.

7. A display device comprising:

plural display elements;

one or more pulse signal generators that generate plural pulse strings for driving said display elements;

and a control means that generates a pulse string with its pulse interval set corresponding to the desired pulse width of said pulse signal, and a pulse assignment signal that assigns the prescribed pulse in said pulse string for each said pulse signal to be generated, and sends said signals to said pulse signal generators;

wherein said pulse signal generator comprises;

a pulse arrival notification means that reports the arrival of the pulse, which is contained in the input pulse string and which is input when an enable signal indicating permission for pulse input is given, together with the information that specifies said pulse;

a pulse arrival judgment means, which uses the pulse assignment signals corresponding to said pulse signals to be generated as input, and which determines whether the pulse assigned with said pulse assignment signal has arrived for each of said pulse signals on the basis of the notification of said pulse arrival notification means;

and a pulse signal output means that inverts the output level of the pulse signal, for which arrival of said assigned pulse is judged by said pulse arrival judgment means, synchronously with the arrival of said pulse.

8. The display device described in claim 7, wherein said pulse arrival judgment means reports the arrival of the pulse that is contained in said pulse string and that is input when an enable signal indicating permission for pulse input is given;

and

wherein said control means outputs said pulse string commonly to plural pulse signal generators, and, at the same time, generates said enable signal, which grants or denies permission for pulse input corresponding to said pulse width in each pulse signal generator, in each pulse cycle of said pulse string.

9. The display device described in claim 7, wherein said pulse arrival judgment means reports the arrival of the pulse that is contained in said pulse string and that is input when an enable signal indicating permission for pulse input is given;

and said control means generates said enable signal that sequentially permits said pulse input for the plural pulse signal generators, and, at the same time, it outputs said pulse string, which sets presence or absence of the pulse in each period where pulse input of said plural pulse signal generators is permitted corresponding to said desired pulse width, commonly to said plural pulse signal generators.

10. The display device described in claim 8 wherein each of said pulse signal generators also includes a first signal holding means that holds the signal input to the first input terminal and outputs the held signal to the first output terminal synchronously with the input clock signal;

said pulse arrival notification means has the signal held in said first signal holding means input to it as said enable signal;

said plural pulse signal generators are connected in cascade via said first input terminals and said first output terminals;

and said control means feeds said enable signals sent to said various stages of pulse signal generators connected in cascade sequentially to the initial stage of said cascade connection synchronously with said clock signal.

11. The display device described in claim 8 wherein each of said pulse signal generators includes a second signal holding means that holds the signal input to a second input terminal and outputs the held signal to a second output terminal synchronously with the input clock signal;

and

a third signal holding means that holds the signal held in said second signal holding means corresponding to the input latch signal;

said pulse arrival notification means has the signal held in said third signal holding means as said pulse indicating signal;

said plural pulse signal generators are connected in cascade via said second input terminals and said second output terminals;

and said control means supplies said pulse indicating signals sent to said various stages of pulse signal generators connected in cascade sequentially to the initial stage of said cascade connection synchronously with said clock signal and generates said latch signal that holds said held signal in said third signal holding means at the timing for holding said pulse indicating signal in said second signal holding means of the pulse signal generator as the supplied object.

12. The display device described in claim 11, wherein said control means generates said clock signal, with one clock pulse, for which the result of the prescribed logic operation with said pulse string becomes a prescribed value, in a prescribed period;

and said pulse signal generator contains a logic operation means that outputs the result of said logic operation between said clock signal and said pulse string as said latch signal.

13. The display device described in claim 12 wherein said pulse arrival notification means counts the pulses that are contained in the pulse string and that are input when said enable signal indicating permission for pulse input is given, and initializes said counting result corresponding to the result of operation of said logic operation means;

said pulse arrival judgment means compares said pulse assignment signal to the counting result of said pulse arrival notification means, and judges the arrival of said assigned pulse corresponding to the comparison result.

14. The display device described in claim 7, further comprising a packet signal processing means, which generates a packet signal containing at least one of said enable signal and/or said pulse assignment signal sent to said pulse signal generators;

respectively, and an identification information that indicates the destination pulse signal generator;

and which determines whether said packet signal is to be received corresponding to said identification information contained in said packet signal, and, when the decision is made for reception, extracts said enable signal and/or said pulse assignment signal from said packet signal.

19. The display device described in claim 9 wherein each of said pulse signal generators includes a second signal holding means that holds the signal input to a second input terminal and outputs the held signal to a second output terminal synchronously with the input clock signal;

and

a third signal holding means that holds the signal held in said second signal holding means corresponding to the input latch signal;

said pulse arrival notification means has the signal held in said third signal holding means as said pulse indicating signal;

said plural pulse signal generators are connected in cascade via said second input terminals and said second output terminals;

and said control means supplies said pulse indicating signals sent to said various stages of pulse signal generators connected in cascade sequentially to the initial stage of said cascade connection synchronously with said clock signal and generates said latch signal that holds said held signal in said third signal holding means at the timing for holding said pulse indicating signal in said second signal holding means of the pulse signal generator as the supplied object.

20. The display device described in claim 10 wherein each of said pulse signal generators includes a second signal holding means that holds the signal input to a second input terminal and outputs the held signal to a second output terminal synchronously with the input clock signal;

and

a third signal holding means that holds the signal held in said second signal holding means corresponding to the input latch signal;

said pulse arrival notification means has the signal held in said third signal holding means as said pulse indicating signal;

said plural pulse signal generators are connected in cascade via said second input terminals and said second output terminals;

and said control means supplies said pulse indicating signals sent to said various stages of pulse signal generators connected in cascade sequentially to the initial stage of said cascade connection synchronously with said clock signal and generates said latch signal that holds said held signal in said third signal holding means at the timing for holding said pulse indicating signal in said second signal holding means of the pulse signal generator as the supplied object.

15. A pulse signal generator comprising:

a pulse signal generator is used to control the logic level of an output pulse signal corresponding to arrival of a pulse signal;

wherein the pulse signal generator comprises a pulse assignment signal holding circuit that holds a pulse assignment signal for assigning one pulse signal in the pulse string supplied during the prescribed period as a response to an initializing signal,

a counting circuit, which resets a count value at a prescribed value as a response to said initialization signal, and which increments or decrements said count value corresponding to input of said pulse signal,

a comparator that compares a value of the pulse assignment signal held in said pulse assignment signal holding circuit with said count value of said counting circuit;

and a pulse signal output circuit that controls a logic level of said output pulse signal in response to a comparison result signal output from said comparator.

16. The pulse signal generator described in claim 15, further comprising

an enable signal holding circuit that holds an enable signal in response to a clock signal;

and a controller that controls supplying said pulse signal to said counting circuit responsive to said enable signal held in said enable signal holding circuit.

17. The pulse signal generator described in claim 15 further comprising a logic circuit that generates said initialization signal on the basis of the first initial pulse signal in the pulse string fed during a prescribed period.

18. The pulse signal generator described in claim 15 wherein the timing of arrival of said pulse signal corresponds to gradation data in the display device.