High-speed serial linking device with de-emphasis function and the method thereof

• US 20050018778A1
• Filed: 05/28/2004
• Published: 01/27/2005
• Est. Priority Date: 07/22/2003
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chang, Chi
• Granted Patent: US 7,313,187 B2
• Time in patent office: Days
• US Class Current: 375/257
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0288 the shape being matched to the transmission line pre-equalisation per se H04L25/03343

Abstract

A high-speed serial linking device with de-emphasis function for receiving a parallel data and accordingly outputting a de-emphasized transmission differential pair. The high-speed serial linking device includes a parallel-to-serial unit, a pre-driver, and an output driver. The parallel-to-serial unit is used to receive a parallel data and further serializes the parallel data into a serial data and a delayed serial data. The pre-driver outputs a data differential pair according to the serial data and outputs a delayed-and-inverted differential pair according to the delayed serial data. The output driver unit is used to receive the data differential pair and the delayed-and-inverted differential pair to accordingly output a de-emphasized transmission differential pair.

Claims

1. A high-speed serial linking device with de-emphasis function, comprising:

a parallel-to-serial unit which receives a parallel data to serialize the parallel data into a serial data and a delayed serial data, wherein the delayed serial data is one serial bit time lag behind the serial data;

a pre-driver which receives the serial data and the delayed serial data to output a data differential pair according to the serial data and output a delayed-and-inverted differential pair according to the delayed serial data, wherein the delayed-and-inverted differential pair is the inverse of and one serial bit time lag behind the data differential pair; and

an output driver unit which receives the data differential pair and the delayed-and-inverted differential pair to output a de-emphasized transmission differential pair.

2. The high-speed serial linking device according to claim 1, wherein the parallel-to-serial unit comprises:

a first serializer which receives and serializes the parallel data to output the serial data;

a register which receives the last bit of the parallel data and further has the last bit of the parallel data delayed and outputted; and

a second serializer which generates and outputs the delayed serial data according to the parallel data and the output of the register.

3. The high-speed serial linking device according to claim 1, wherein the pre-driver comprises:

a data differentiator which receives the serial data and accordingly outputs the data differential pair; and

an inverse data differentiator which receives the delayed serial data and outputs the delayed-and-inverted differential pair.

4. The high-speed serial linking device according to claim 3, wherein the data differentiator comprises:

an AND gate which receives a first control signal and the serial data and outputs a positive differential signal of the data differential pair; and

an NOR gate which receives a second control signal and the serial data and outputs a negative differential signal of the data differential pair, wherein the first control signal is the inverse of the second control signal.

5. The high-speed serial linking device according to claim 3, wherein the inverse data differentiator comprises:

an AND gate which receives a first control signal and the delayed serial data and outputs a negative differential signal of the delayed-and-inverted differential pair; and

an NOR gate which receives a second control signal and the delayed serial data and accordingly outputs a positive differential signal of the delayed-and-inverted differential pair, wherein the first control signal is the inverse of the second control signal.

6. The high-speed serial linking device according to claim 1, wherein the output driver comprises:

a first output circuit which receives a positive delayed-and-inverted differential signal of the data differential pair and a positive differential signal of the delayed-and-inverted differential pair to output a positive transmission differential signal of the de-emphasized transmission differential pair; and

a second output circuit which receives a negative differential signal of the data differential pair and a negative delayed-and-inverted differential signal of the delayed-and-inverted differential pair to output a negative transmission differential signal of the de-emphasized transmission differential pair.

7. The high-speed serial linking device according to claim 6, wherein the first output circuit comprises:

a first current source;

a second current source;

a resistor;

a first switch which decides if the current of the first current source is allowed to flow to the resistor according to the positive differential signal of the data differential pair; and

a second switch which decides if the current of the second current source is allowed to flow to the resistor according to the positive delayed-and-inverted differential signal of the delayed-and-inverted differential pair.

8. The high-speed serial linking device according to claim 7, wherein the first switch and the second switch are transistors.

9. The high-speed serial linking device according to claim 7, wherein the current of the first current source is larger than the current of the second current source.

10. The high-speed serial linking device according to claim 6, wherein the second output circuit comprises:

a first current source;

a second current source;

a resistor;

a first switch which decides if the current of the first current source is allowed to flow to the resistor according to the negative differential signal of the data differential pair; and

a second switch which decides if the current of the second current source is allowed to flow to the resistor according to the negative delayed-and-inverted differential signal of the delayed-and-inverted differential pair.

11. The high-speed serial linking device according to claim 10, wherein the first switch and the second switch are transistors.

12. The high-speed serial linking device according to claim 10, wherein the current of the first current source is larger than the current of the second current source.

13. A high-speed serial linking transmission method with de-emphasis function, comprising the steps of:

serializing a parallel data into a serial data and a delayed serial data, wherein the delayed serial data is one serial bit time lag behind the serial data;

converting the serial data and the delayed serial data into a data differential pair and a delayed-and-inverted differential pair respectively, wherein the delayed-and-inverted differential pair is the inverse of and is one serial bit time lag behind the data differential pair; and

generating a de-emphasized transmission differential pair according to the data differential pair and the delayed-and-inverted differential pair.

14. The method according to claim 13, wherein a positive transmission differential signal of and a negative transmission differential signal of the de-emphasized transmission differential pair respectively belongs to one of the four levels ranked in a descending order, namely level 1, level 2, level 3 and level 4.

15. The method according to claim 13, wherein the serializing step comprises:

serializing the parallel data into a serial data;

storing the last bit of the parallel data and outputting it after a serial bit time; and

generating a delayed serial data which is one serial bit time lag behind the serial data.

16. The method according to claim 13, wherein the generation of the data differential pair comprises:

performing AND operation on a first control signal and the serial data to generate a positive differential signal of the data differential pair; and

performing NOR operation on a second control signal and the serial data to generate a negative differential signal of the data differential pair, wherein the second control signal is the inverse of the first control signal.

17. The method according to claim 13, wherein the generation of the delayed-and-inverted differential pair comprises the steps of:

performing AND operation on a first control signal and the delayed serial data to generate a negative delayed-and-inverted differential signal of the delayed-and-inverted differential pair; and

performing NOR operation on a second control signal and the delayed serial data to generate a positive delayed-and-inverted differential signal of the delayed-and-inverted differential pair, wherein the second control signal is the inverse of the first control signal.

18. The method according to claim 13, wherein the generation of the de-emphasized transmission differential pair comprises:

generating a positive transmission signal of the de-emphasized transmission differential pair according to a positive differential signal of the data differential pair and a positive delayed-and-inverted differential signal of the delayed-and-inverted differential pair; and

generating a negative transmission signal of the de-emphasized transmission differential pair according to a negative differential signal of the data differential pair and a negative delayed-and-inverted differential signal of the delayed-and-inverted differential pair.