SELF-CONTAINED PROCESSOR SUBSYSTEM AS COMPONENT FOR SYSTEM-ON-CHIP DESIGN
First Claim
1. A microprocessor subsystem for use in a system-on-chip (SoC) integrated circuit (IC) comprising a communications bus device, said microprocessor sub-system comprising:
- two or more microprocessor devices formed as a single processor core assembly and capable of performing operations to implement a given processing functionality;
a memory storage device associated with said two or more microprocessor devices in said sub-system for storing at least one of data and instructions in said single processor core assembly;
an interconnect means residing in said single processor core assembly for enabling communication between said two or more microprocessor devices and said SoC IC communications bus device, whereby said single processor core assembly may communicate with components of said SoC IC.
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Accused Products
Abstract
A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.
88 Citations
30 Claims
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1. A microprocessor subsystem for use in a system-on-chip (SoC) integrated circuit (IC) comprising a communications bus device, said microprocessor sub-system comprising:
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two or more microprocessor devices formed as a single processor core assembly and capable of performing operations to implement a given processing functionality;
a memory storage device associated with said two or more microprocessor devices in said sub-system for storing at least one of data and instructions in said single processor core assembly;
an interconnect means residing in said single processor core assembly for enabling communication between said two or more microprocessor devices and said SoC IC communications bus device, whereby said single processor core assembly may communicate with components of said SoC IC. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A system-on-chip (SoC) Integrated Circuit (IC) network processor architecture comprising:
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a network processor core for controlling SoC network processor functions among a plurality of network processor components;
an SoC local system bus device for enabling communications among said SoC network processor components, one SoC network processor component comprising an independent multiprocessor subsystem core comprising;
i) at least one microprocessor implementing a given functionality;
ii) at least one memory storage device for storing at least one of data and instructions; and
iii) interconnect means for enabling high speed communication between two or more microprocessor devices and said SoC IC local system bus device, wherein said single SoC multiprocessor subsystem core provides multi-threading network processing capability. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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23. A system-on-chip (SoC) processor Integrated Circuit (IC) architecture comprising:
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a processor core for controlling SoC processing functions among a plurality of SoC component devices;
an SoC local system bus device for enabling communications among said SoC component devices, one SoC component device comprising a single independent multiprocessor subsystem core comprising;
a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and
a switch fabric means connecting each processor cluster within said SoC IC, wherein said single SoC multiprocessor subsystem core is capable of performing multi-threading operation processing. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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Specification