Multiple oxide thicknesses for merged memory and logic applications
First Claim
1. A semiconductor device, comprising:
- a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the logic device having a logic gate separated from the top surface by a logic gate oxide; and
an EEPROM (Electronically Erasable Programmable Read Only Memory) device formed on a trench wall of the silicon wafer, the EEPROM device having an EEPROM gate separated from the trench wall by a EEPROM gate oxide, wherein the trench wall has a different order plane-orientation than top surface and wherein a thickness of the logic gate oxide is different from a thickness of the EEPROM gate oxide.
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Accused Products
Abstract
Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2 on a top surface of a silicon wafer and a trench layer of SiO2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.
45 Citations
38 Claims
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1. A semiconductor device, comprising:
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a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the logic device having a logic gate separated from the top surface by a logic gate oxide; and
an EEPROM (Electronically Erasable Programmable Read Only Memory) device formed on a trench wall of the silicon wafer, the EEPROM device having an EEPROM gate separated from the trench wall by a EEPROM gate oxide, wherein the trench wall has a different order plane-orientation than top surface and wherein a thickness of the logic gate oxide is different from a thickness of the EEPROM gate oxide. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An electronic system comprising:
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a processor; and
an integrated circuit coupled to the processor, the integrated circuit including;
a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (8, 9, 10, 11)
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12. An electronic system comprising:
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a processor; and
a flash memory device including;
a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (111) crystal plane orientation, the logic device having a logic gate separated from the top surface by a logic gate oxide; and
a flash memory cell formed on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystal plane orientation, the flash memory cell having a flash gate separated from the trench wall by a flash gate oxide, wherein a thickness of the flash gate oxide is different from the logic gate oxide. - View Dependent Claims (13, 14, 15, 16, 17)
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18. An electronic system comprising:
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a processor; and
a decode circuit, comprising;
a logic circuit formed on a top surface of a silicon wafer, wherein the top layer has a (110) crystal plane orientation, the logic circuit having a logic gate separated from the top layer by a logic gate oxide; and
an EEPROM (Electronically Erasable Programmable Read Only Memory) device formed on a trench wall of the silicon wafer, the EEPROM device having an EEPROM gate separated from the trench wall by a EEPROM gate oxide, wherein the trench wall has a different order plane-orientation than top surface and wherein a thickness of the EEPROM gate oxide is different from a thickness of the logic gate oxide. - View Dependent Claims (19, 20, 21, 22)
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23. A semiconductor device, comprising;
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a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide; and
an EEPROM device formed on a trench wall of the silicon wafer, the trench wall having a (110) crystal plane orientation and a trench gate oxide. - View Dependent Claims (24, 25)
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26. A semiconductor device, comprising;
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a logic device formed on a top surface of a silicon wafer having a (111) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (110) crystal plane orientation and a trench gate oxide. - View Dependent Claims (27)
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28. A semiconductor device, comprising;
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a logic device formed on a top surface of a silicon wafer having a (111) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (311) crystal plane orientation and a trench gate oxide. - View Dependent Claims (29)
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30. An electronic system, comprising;
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a processor; and
an integrated circuit coupled to the processor, the integrated circuit including;
a logic device formed on a top surface of a silicon wafer having a (111) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (511) crystal plane orientation and a trench gate oxide. - View Dependent Claims (31)
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32. An electronic system, comprising;
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a processor; and
an integrated circuit coupled to the processor, the integrated circuit including;
a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (110) crystal plane orientation and a trench gate oxide. - View Dependent Claims (33)
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34. An electronic system, comprising;
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a processor; and
a decode circuit, comprising;
a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (110) crystal plane orientation and a trench gate oxide. - View Dependent Claims (35)
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36. An electronic system, comprising;
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a processor; and
a decode circuit, comprising;
a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (311) crystal plane orientation and a trench gate oxide. - View Dependent Claims (37)
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38. An electronic system, comprising;
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a processor; and
a decode circuit, comprising;
a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide; and
a memory device formed on a trench wall of the silicon wafer, the trench wall having a (511) crystal plane orientation and a trench gate oxide. 39. The semiconductor device of claim 38 further comprising the trench gate oxide is different from the top gate oxide, and the top gate oxide and the trench gate oxide are formed simultaneously.
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Specification