Test signal distribution system for IC tester

• US 20050024070A1
• Filed: 08/30/2004
• Published: 02/03/2005
• Est. Priority Date: 05/08/2002
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Granted Patent: US 7,012,442 B2
• Time in Patent Office: Days
• US Class Current: 324/756.30
• CPC Class Codes: G01R 1/06772 High frequency probes
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture

Abstract

A probe board provides signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. A branching signal path within the probe board distributes a test signal produced by one channel of the IC tester to several probes. Resistors within the branching signal path resistively isolate the probes from one another so that a fault occurring at any one IC terminal will not affect the logic state of the test signal arriving at any other IC terminal. The isolation resistors are sized relative to signal path characteristic impedances so as to substantially minimize test signal reflections at the branch points.

Claims

1-32. -32:

(Canceled)

33. :

A probe substrate comprising;

a substrate;

a plurality of electrically conductive terminals disposed on a first side of said substrate;

a plurality of electrically conductive probes disposed on a second side of said substrate and disposed to correspond to terminals of an electrical device to be tested, wherein said first side is opposite said second side;

a plurality of electrically conductive paths electrically connecting ones of said terminals with ones of said probes; and

a plurality of resistors disposed on said substrate, ones of said resistors electrically connected to ones of said conductive paths.

34. :

The probe substrate of claim 33, wherein said substrate is a space transformer.

35. :

The probe substrate of claim 33, wherein;

said terminals are disposed in a first pitch,

said probes are disposed in a second pitch, and

said second pitch is tighter than said first pitch.

36. :

The probe substrate of claim 33, wherein ones of said terminals are disposed to receive test signals generated by a tester for testing said electronic device.

37. :

The probe substrate of claim 36, wherein;

said electronic device is a semiconductor die, and

said tester is a semiconductor die tester.

38. :

The probe substrate of claim 36, wherein said semiconductor die composes a semiconductor wafer that comprises a plurality of semiconductor dies.

39. :

The probe substrate of claim 33, wherein;

multiple ones of said conductive paths electrically connect one of said terminals with multiple ones of said probes, and

one of said resistors is disposed within each said conductive path providing resistive isolation of one probe from another probe.

40. :

The probe substrate of claim 33, wherein said ones of said resistors are disposed within said ones of said conductive paths and comprise resistance within said ones of said conductive paths.